Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.08	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	32	96	75.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	32	96	75.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2662

1

T5

10

T8

4

T9

4

auto[1]

1002

1

T3

30

T60

10

T70

14

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	562	1			T3	30		T8	4		T9	4
values[1]	514	1			T5	10		T52	12		T183	4
values[2]	384	1			T69	24		T92	8		T100	22
values[3]	388	1			T12	30		T79	4		T68	30
values[4]	458	1			T60	10		T182	2		T103	4
values[5]	422	1			T26	6		T186	22		T274	12
values[6]	374	1			T13	2		T119	12		T74	30
values[7]	562	1			T29	12		T50	6		T97	10

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	370	1			T9	4		T52	12		T20	6
values[1]	516	1			T51	8		T97	10		T194	20
values[2]	332	1			T13	2		T100	22		T183	4
values[3]	704	1			T12	30		T79	4		T68	30
values[4]	416	1			T3	30		T8	4		T73	22
values[5]	382	1			T5	10		T119	12		T187	12
values[6]	340	1			T182	2		T184	20		T185	18
values[7]	604	1			T60	10		T70	14		T69	24

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	32	96	75.00	32

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[5] , values[6]]	[values[1]]	--	--	2
[auto[1]]	[values[0]]	[values[0]]	0	1	1
[auto[1]]	[values[0]]	[values[2]]	0	1	1
[auto[1]]	[values[1]]	[values[3] , values[4] , values[5] , values[6]]	--	--	4
[auto[1]]	[values[2]]	[values[0]]	0	1	1
[auto[1]]	[values[2]]	[values[2]]	0	1	1
[auto[1]]	[values[2]]	[values[4]]	0	1	1
[auto[1]]	[values[2]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[3]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[3]]	[values[5]]	0	1	1
[auto[1]]	[values[4]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[4]]	[values[4] , values[5] , values[6]]	--	--	3
[auto[1]]	[values[5]]	[values[0]]	0	1	1
[auto[1]]	[values[6]]	[values[0]]	0	1	1
[auto[1]]	[values[6]]	[values[4]]	0	1	1
[auto[1]]	[values[6]]	[values[6]]	0	1	1
[auto[1]]	[values[7]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[7]]	[values[3] , values[4] , values[5]]	--	--	3

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	52	1			T9	4		T20	6		T268	24
auto[0]	values[0]	values[1]	70	1			T51	8		T242	8		T205	6
auto[0]	values[0]	values[2]	10	1			T251	4		T314	6		-	-
auto[0]	values[0]	values[3]	98	1			T282	22		T287	12		T276	10
auto[0]	values[0]	values[4]	22	1			T8	4		T252	18		-	-
auto[0]	values[0]	values[5]	44	1			T227	8		T315	6		T316	2
auto[0]	values[0]	values[6]	18	1			T185	18		-	-		-	-
auto[0]	values[0]	values[7]	54	1			T201	2		T127	18		T285	28
auto[0]	values[1]	values[0]	42	1			T52	12		T317	8		T283	22
auto[0]	values[1]	values[1]	42	1			T265	10		T318	8		T284	24
auto[0]	values[1]	values[2]	34	1			T183	4		T27	2		T209	18
auto[0]	values[1]	values[3]	80	1			T76	34		T202	12		T195	34
auto[0]	values[1]	values[4]	62	1			T200	2		T32	36		T237	14
auto[0]	values[1]	values[5]	60	1			T5	10		T187	12		T126	30
auto[0]	values[1]	values[6]	28	1			T281	8		T269	20		-	-
auto[0]	values[1]	values[7]	26	1			T239	2		T319	4		T320	20
auto[0]	values[2]	values[0]	8	1			T92	8		-	-		-	-
auto[0]	values[2]	values[1]	36	1			T261	10		T125	4		T264	16
auto[0]	values[2]	values[2]	62	1			T100	22		T28	6		T217	6
auto[0]	values[2]	values[3]	30	1			T229	20		T321	10		-	-
auto[0]	values[2]	values[4]	14	1			T189	14		-	-		-	-
auto[0]	values[2]	values[5]	12	1			T171	12		-	-		-	-
auto[0]	values[2]	values[6]	36	1			T241	10		T322	26		-	-
auto[0]	values[2]	values[7]	120	1			T69	24		T188	14		T221	20
auto[0]	values[3]	values[0]	48	1			T323	14		T324	34		-	-
auto[0]	values[3]	values[1]	54	1			T262	20		T191	20		T325	10
auto[0]	values[3]	values[2]	50	1			T180	28		T222	22		-	-
auto[0]	values[3]	values[3]	40	1			T12	30		T79	4		T81	6
auto[0]	values[3]	values[4]	30	1			T235	8		T203	22		-	-
auto[0]	values[3]	values[5]	10	1			T272	10		-	-		-	-
auto[0]	values[3]	values[6]	14	1			T193	14		-	-		-	-
auto[0]	values[3]	values[7]	34	1			T101	18		T208	12		T243	4
auto[0]	values[4]	values[0]	30	1			T225	4		T121	18		T197	8
auto[0]	values[4]	values[1]	84	1			T294	14		T236	20		T266	4
auto[0]	values[4]	values[2]	26	1			T253	26		-	-		-	-
auto[0]	values[4]	values[3]	102	1			T102	26		T207	28		T80	14
auto[0]	values[4]	values[4]	22	1			T73	22		-	-		-	-
auto[0]	values[4]	values[5]	18	1			T250	18		-	-		-	-
auto[0]	values[4]	values[6]	64	1			T182	2		T98	24		T259	26
auto[0]	values[4]	values[7]	10	1			T103	4		T326	6		-	-
auto[0]	values[5]	values[0]	36	1			T128	16		T290	20		-	-
auto[0]	values[5]	values[2]	32	1			T186	22		T30	10		-	-
auto[0]	values[5]	values[3]	18	1			T286	18		-	-		-	-
auto[0]	values[5]	values[4]	38	1			T271	16		T233	12		T220	10
auto[0]	values[5]	values[5]	24	1			T274	12		T211	8		T327	4
auto[0]	values[5]	values[6]	12	1			T226	12		-	-		-	-
auto[0]	values[5]	values[7]	82	1			T26	6		T328	18		T289	10
auto[0]	values[6]	values[0]	26	1			T199	18		T329	8		-	-
auto[0]	values[6]	values[2]	30	1			T13	2		T216	16		T198	12
auto[0]	values[6]	values[3]	20	1			T105	20		-	-		-	-
auto[0]	values[6]	values[4]	38	1			T104	22		T31	8		T53	8
auto[0]	values[6]	values[5]	68	1			T119	12		T54	14		T330	32
auto[0]	values[6]	values[6]	44	1			T74	30		T331	14		-	-
auto[0]	values[6]	values[7]	12	1			T223	12		-	-		-	-
auto[0]	values[7]	values[0]	74	1			T332	14		T196	4		T7	20
auto[0]	values[7]	values[1]	50	1			T97	10		T194	20		T232	18
auto[0]	values[7]	values[2]	26	1			T218	26		-	-		-	-
auto[0]	values[7]	values[3]	62	1			T29	12		T50	6		T333	20
auto[0]	values[7]	values[4]	92	1			T273	26		T248	4		T260	20
auto[0]	values[7]	values[5]	46	1			T254	32		T334	14		-	-
auto[0]	values[7]	values[6]	68	1			T184	20		T256	32		T247	16
auto[0]	values[7]	values[7]	68	1			T206	20		T291	22		T299	26
auto[1]	values[0]	values[1]	20	1			T244	2		T89	18		-	-
auto[1]	values[0]	values[3]	70	1			T72	36		T84	32		T263	2
auto[1]	values[0]	values[4]	56	1			T3	30		T75	22		T335	4
auto[1]	values[0]	values[5]	30	1			T336	30		-	-		-	-
auto[1]	values[0]	values[6]	4	1			T337	4		-	-		-	-
auto[1]	values[0]	values[7]	14	1			T70	14		-	-		-	-
auto[1]	values[1]	values[0]	54	1			T298	20		T338	34		-	-
auto[1]	values[1]	values[1]	34	1			T292	34		-	-		-	-
auto[1]	values[1]	values[2]	30	1			T255	30		-	-		-	-
auto[1]	values[1]	values[7]	22	1			T293	22		-	-		-	-
auto[1]	values[2]	values[1]	26	1			T231	26		-	-		-	-
auto[1]	values[2]	values[3]	14	1			T339	14		-	-		-	-
auto[1]	values[2]	values[5]	26	1			T78	6		T219	20		-	-
auto[1]	values[3]	values[3]	60	1			T68	30		T94	30		-	-
auto[1]	values[3]	values[4]	20	1			T224	20		-	-		-	-
auto[1]	values[3]	values[6]	12	1			T228	12		-	-		-	-
auto[1]	values[3]	values[7]	16	1			T204	16		-	-		-	-
auto[1]	values[4]	values[3]	48	1			T83	16		T340	32		-	-
auto[1]	values[4]	values[7]	54	1			T60	10		T341	32		T342	12
auto[1]	values[5]	values[1]	68	1			T77	30		T238	24		T213	12
auto[1]	values[5]	values[2]	10	1			T82	10		-	-		-	-
auto[1]	values[5]	values[3]	30	1			T257	30		-	-		-	-
auto[1]	values[5]	values[4]	22	1			T297	22		-	-		-	-
auto[1]	values[5]	values[5]	22	1			T215	22		-	-		-	-
auto[1]	values[5]	values[6]	6	1			T280	6		-	-		-	-
auto[1]	values[5]	values[7]	22	1			T210	22		-	-		-	-
auto[1]	values[6]	values[1]	32	1			T343	32		-	-		-	-
auto[1]	values[6]	values[2]	8	1			T344	8		-	-		-	-
auto[1]	values[6]	values[3]	32	1			T245	6		T295	26		-	-
auto[1]	values[6]	values[5]	22	1			T87	22		-	-		-	-
auto[1]	values[6]	values[7]	42	1			T85	36		T86	6		-	-
auto[1]	values[7]	values[2]	14	1			T71	14		-	-		-	-
auto[1]	values[7]	values[6]	34	1			T296	34		-	-		-	-
auto[1]	values[7]	values[7]	28	1			T88	28		-	-		-	-