Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	128	1			T12	4		T20	2		T50	2
auto[ReadAddrCrossIntoMailbox]	28	1			T13	2		T92	2		T241	2
auto[ReadAddrCrossOutOfMailbox]	30	1			T12	12		T208	2		T198	4
auto[ReadAddrCrossAllMailbox]	48	1			T5	6		T12	8		T92	4
auto[ReadAddrOutsideMailbox]	920	1			T3	4		T5	4		T12	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

577

1

T3

2

T5

5

T12

15

auto[1]

577

1

T3

2

T5

5

T12

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	226	1			T12	8		T79	2		T94	2
read_ops[0x0b]	238	1			T5	2		T12	6		T92	4
read_ops[0x3b]	184	1			T12	6		T20	2		T69	2
read_ops[0x6b]	114	1			T5	2		T12	6		T92	4
read_ops[0xbb]	194	1			T69	2		T94	2		T185	4
read_ops[0xeb]	198	1			T3	4		T5	6		T12	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	17	1			T50	1		T188	1		T208	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	17	1			T50	1		T188	1		T208	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T197	1		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T197	1		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	6	1			T12	3		T198	1		T233	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	6	1			T12	3		T198	1		T233	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	5	1			T12	1		T171	1		T208	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	5	1			T12	1		T171	1		T208	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	84	1			T79	1		T94	1		T185	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	84	1			T79	1		T94	1		T185	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	9	1			T188	1		T53	1		T121	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	9	1			T188	1		T53	1		T121	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T261	1		T198	1		T247	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T261	1		T198	1		T247	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T12	1		T247	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T12	1		T247	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	5	1			T5	1		T12	1		T92	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	5	1			T5	1		T12	1		T92	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	100	1			T12	1		T92	1		T51	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	100	1			T12	1		T92	1		T51	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	14	1			T12	1		T20	1		T261	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	14	1			T12	1		T20	1		T261	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	4	1			T261	2		T247	2		-	-
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	4	1			T261	2		T247	2		-	-
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T208	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T208	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	5	1			T12	1		T171	1		T328	3
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	5	1			T12	1		T171	1		T328	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	68	1			T12	1		T69	1		T194	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	68	1			T12	1		T69	1		T194	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	6	1			T12	1		T121	2		T329	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	6	1			T12	1		T121	2		T329	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T92	1		T171	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T92	1		T171	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T12	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T12	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T5	1		T92	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T5	1		T92	1		-	-
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	46	1			T12	1		T94	1		T97	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	46	1			T12	1		T94	1		T97	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	9	1			T188	1		T208	2		T226	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	9	1			T188	1		T208	2		T226	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T241	1		T233	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T241	1		T233	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T198	1		T328	1		T267	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T198	1		T328	1		T267	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T198	1		T279	1		T233	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T198	1		T279	1		T233	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	79	1			T69	1		T94	1		T185	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	79	1			T69	1		T94	1		T185	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	9	1			T171	1		T271	1		T121	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	9	1			T171	1		T271	1		T121	3
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T13	1		T171	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T13	1		T171	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T12	1		T328	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T12	1		T328	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T5	1		T12	1		T328	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T5	1		T12	1		T328	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	83	1			T3	2		T5	2		T60	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	83	1			T3	2		T5	2		T60	3