Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	270713	1			T1	1		T2	1		T3	1
all_pins[1]	270713	1			T1	1		T2	1		T3	1
all_pins[2]	270713	1			T1	1		T2	1		T3	1
all_pins[3]	270713	1			T1	1		T2	1		T3	1
all_pins[4]	270713	1			T1	1		T2	1		T3	1
all_pins[5]	270713	1			T1	1		T2	1		T3	1
all_pins[6]	270713	1			T1	1		T2	1		T3	1
all_pins[7]	270713	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2164792	1			T1	8		T2	8		T3	8
values[0x1]	912	1			T44	25		T45	53		T46	13
transitions[0x0=>0x1]	684	1			T44	17		T45	44		T46	11
transitions[0x1=>0x0]	696	1			T44	17		T45	44		T46	12

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	270594	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	119	1			T45	6		T46	1		T361	11
all_pins[0]	transitions[0x0=>0x1]	96	1			T45	6		T46	1		T361	9
all_pins[0]	transitions[0x1=>0x0]	87	1			T44	5		T45	9		T46	2
all_pins[1]	values[0x0]	270603	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	110	1			T44	5		T45	9		T46	2
all_pins[1]	transitions[0x0=>0x1]	88	1			T44	3		T45	7		T46	2
all_pins[1]	transitions[0x1=>0x0]	83	1			T44	1		T45	2		T46	3
all_pins[2]	values[0x0]	270608	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	105	1			T44	3		T45	4		T46	3
all_pins[2]	transitions[0x0=>0x1]	71	1			T44	2		T45	4		T46	3
all_pins[2]	transitions[0x1=>0x0]	86	1			T45	5		T46	1		T361	4
all_pins[3]	values[0x0]	270593	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	120	1			T44	1		T45	5		T46	1
all_pins[3]	transitions[0x0=>0x1]	83	1			T45	3		T46	1		T361	4
all_pins[3]	transitions[0x1=>0x0]	86	1			T44	3		T45	5		T46	2
all_pins[4]	values[0x0]	270590	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	123	1			T44	4		T45	7		T46	2
all_pins[4]	transitions[0x0=>0x1]	103	1			T44	2		T45	6		T46	2
all_pins[4]	transitions[0x1=>0x0]	74	1			T44	3		T45	6		T361	3
all_pins[5]	values[0x0]	270619	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	94	1			T44	5		T45	7		T361	3
all_pins[5]	transitions[0x0=>0x1]	72	1			T44	4		T45	5		T361	3
all_pins[5]	transitions[0x1=>0x0]	89	1			T44	1		T45	3		T46	2
all_pins[6]	values[0x0]	270602	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	111	1			T44	2		T45	5		T46	2
all_pins[6]	transitions[0x0=>0x1]	79	1			T44	1		T45	4		T46	2
all_pins[6]	transitions[0x1=>0x0]	98	1			T44	4		T45	9		T46	2
all_pins[7]	values[0x0]	270583	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	130	1			T44	5		T45	10		T46	2
all_pins[7]	transitions[0x0=>0x1]	92	1			T44	5		T45	9		T361	4
all_pins[7]	transitions[0x1=>0x0]	93	1			T45	5		T361	9		T362	2