Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
65.07	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	51	77	60.16

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	51	77	60.16	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	528	1			T9	4		T12	30		T52	12
values[1]	454	1			T3	30		T182	2		T183	4
values[2]	542	1			T50	6		T51	8		T184	20
values[3]	498	1			T68	30		T94	30		T29	12
values[4]	358	1			T5	10		T97	10		T180	28
values[5]	486	1			T8	4		T119	12		T70	14
values[6]	328	1			T13	2		T103	4		T73	22
values[7]	470	1			T60	10		T69	24		T92	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	568	1			T8	4		T9	4		T50	6
values[1]	532	1			T69	24		T185	18		T27	2
values[2]	490	1			T68	30		T51	8		T180	28
values[3]	416	1			T5	10		T20	6		T103	4
values[4]	342	1			T100	22		T74	30		T186	22
values[5]	390	1			T3	30		T52	12		T60	10
values[6]	352	1			T12	30		T119	12		T183	4
values[7]	574	1			T13	2		T70	14		T182	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3604

1

T3

30

T5

10

T8

4

auto[1]

60

1

T68

16

T71

2

T72

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	51	77	60.16	51

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[6]]	*	--	--	8

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	[values[1] , values[2] , values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	7
[auto[1]]	[values[1]]	[values[0]]	0	1	1
[auto[1]]	[values[1]]	[values[2] , values[3] , values[4] , values[5] , values[6]]	--	--	5
[auto[1]]	[values[2]]	[values[2] , values[3] , values[4] , values[5]]	--	--	4
[auto[1]]	[values[3]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[3]]	[values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	5
[auto[1]]	[values[4]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[4]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[5]]	[values[1] , values[2] , values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	7
[auto[1]]	[values[7]]	[values[0] , values[1] , values[2] , values[3] , values[4]]	--	--	5
[auto[1]]	[values[7]]	[values[6] , values[7]]	--	--	2

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	68	1			T9	4		T187	12		T84	26
auto[0]	values[0]	values[1]	50	1			T188	14		T189	14		T190	22
auto[0]	values[0]	values[2]	90	1			T191	20		T192	32		T193	14
auto[0]	values[0]	values[3]	60	1			T20	6		T194	20		T195	34
auto[0]	values[0]	values[4]	22	1			T196	4		T82	10		T197	8
auto[0]	values[0]	values[5]	56	1			T52	12		T198	12		T199	18
auto[0]	values[0]	values[6]	42	1			T12	30		T200	2		T201	2
auto[0]	values[0]	values[7]	134	1			T202	12		T203	22		T204	16
auto[0]	values[1]	values[0]	26	1			T205	6		T206	20		-	-
auto[0]	values[1]	values[1]	106	1			T207	28		T208	12		T209	18
auto[0]	values[1]	values[2]	30	1			T210	22		T211	8		-	-
auto[0]	values[1]	values[3]	32	1			T31	8		T54	14		T212	10
auto[0]	values[1]	values[4]	46	1			T213	12		T214	12		T215	22
auto[0]	values[1]	values[5]	98	1			T3	30		T171	12		T216	16
auto[0]	values[1]	values[6]	10	1			T183	4		T217	6		-	-
auto[0]	values[1]	values[7]	96	1			T182	2		T83	14		T218	26
auto[0]	values[2]	values[0]	34	1			T50	6		T219	18		T220	10
auto[0]	values[2]	values[1]	140	1			T27	2		T72	32		T221	20
auto[0]	values[2]	values[2]	30	1			T51	8		T222	22		-	-
auto[0]	values[2]	values[3]	116	1			T223	12		T224	20		T225	4
auto[0]	values[2]	values[4]	34	1			T186	22		T226	12		-	-
auto[0]	values[2]	values[5]	8	1			T227	8		-	-		-	-
auto[0]	values[2]	values[6]	72	1			T71	12		T228	12		T229	20
auto[0]	values[2]	values[7]	96	1			T184	20		T230	16		T231	22
auto[0]	values[3]	values[0]	56	1			T232	18		T233	12		T234	2
auto[0]	values[3]	values[1]	86	1			T235	8		T236	20		T237	14
auto[0]	values[3]	values[2]	96	1			T68	14		T101	18		T81	6
auto[0]	values[3]	values[3]	62	1			T238	24		T239	2		T240	36
auto[0]	values[3]	values[4]	90	1			T100	22		T74	30		T241	10
auto[0]	values[3]	values[5]	20	1			T26	6		T242	8		T243	4
auto[0]	values[3]	values[6]	10	1			T244	2		T245	6		T246	2
auto[0]	values[3]	values[7]	58	1			T94	30		T29	12		T247	16
auto[0]	values[4]	values[0]	74	1			T97	10		T248	4		T249	34
auto[0]	values[4]	values[1]	34	1			T185	18		T89	16		-	-
auto[0]	values[4]	values[2]	58	1			T180	28		T250	18		T251	4
auto[0]	values[4]	values[3]	10	1			T5	10		-	-		-	-
auto[0]	values[4]	values[4]	56	1			T104	22		T252	18		T86	4
auto[0]	values[4]	values[5]	58	1			T253	26		T254	32		-	-
auto[0]	values[4]	values[6]	22	1			T75	22		-	-		-	-
auto[0]	values[4]	values[7]	40	1			T78	6		T125	4		T255	30
auto[0]	values[5]	values[0]	128	1			T8	4		T256	32		T257	30
auto[0]	values[5]	values[1]	48	1			T80	14		T258	4		T259	26
auto[0]	values[5]	values[2]	30	1			T260	20		T261	10		-	-
auto[0]	values[5]	values[3]	80	1			T262	20		T263	2		T264	16
auto[0]	values[5]	values[4]	16	1			T265	10		T266	4		T267	2
auto[0]	values[5]	values[5]	52	1			T268	24		T269	20		T270	8
auto[0]	values[5]	values[6]	68	1			T119	12		T77	30		T271	16
auto[0]	values[5]	values[7]	60	1			T70	14		T79	4		T272	10
auto[0]	values[6]	values[0]	144	1			T73	22		T273	26		T274	12
auto[0]	values[6]	values[1]	2	1			T275	2		-	-		-	-
auto[0]	values[6]	values[2]	20	1			T276	10		T277	10		-	-
auto[0]	values[6]	values[3]	28	1			T103	4		T278	24		-	-
auto[0]	values[6]	values[4]	18	1			T279	4		T280	6		T281	8
auto[0]	values[6]	values[5]	44	1			T282	22		T283	22		-	-
auto[0]	values[6]	values[6]	52	1			T284	24		T285	28		-	-
auto[0]	values[6]	values[7]	20	1			T13	2		T286	18		-	-
auto[0]	values[7]	values[0]	24	1			T287	12		T288	12		-	-
auto[0]	values[7]	values[1]	54	1			T69	24		T289	10		T290	20
auto[0]	values[7]	values[2]	116	1			T291	22		T121	18		T292	34
auto[0]	values[7]	values[3]	28	1			T6	28		-	-		-	-
auto[0]	values[7]	values[4]	58	1			T30	10		T102	26		T293	22
auto[0]	values[7]	values[5]	52	1			T60	10		T92	8		T181	2
auto[0]	values[7]	values[6]	74	1			T294	14		T76	34		T28	6
auto[0]	values[7]	values[7]	62	1			T32	36		T295	26		-	-
auto[1]	values[0]	values[0]	6	1			T84	6		-	-		-	-
auto[1]	values[1]	values[1]	6	1			T296	6		-	-		-	-
auto[1]	values[1]	values[7]	4	1			T83	2		T297	2		-	-
auto[1]	values[2]	values[0]	2	1			T219	2		-	-		-	-
auto[1]	values[2]	values[1]	4	1			T72	4		-	-		-	-
auto[1]	values[2]	values[6]	2	1			T71	2		-	-		-	-
auto[1]	values[2]	values[7]	4	1			T231	4		-	-		-	-
auto[1]	values[3]	values[2]	20	1			T68	16		T88	4		-	-
auto[1]	values[4]	values[0]	2	1			T298	2		-	-		-	-
auto[1]	values[4]	values[1]	2	1			T89	2		-	-		-	-
auto[1]	values[4]	values[4]	2	1			T86	2		-	-		-	-
auto[1]	values[5]	values[0]	4	1			T85	4		-	-		-	-
auto[1]	values[7]	values[5]	2	1			T87	2		-	-		-	-