Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1559

1

T1

6

T16

15

T18

2

auto[1]

1511

1

T1

7

T2

4

T16

11

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

713

1

T16

23

T18

2

T21

14

auto[1]

2357

1

T1

13

T2

4

T16

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2812

1

T1

13

T2

4

T16

17

auto[1]

258

1

T16

9

T18

1

T21

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	651	1			T1	2		T16	6		T19	9
valid[1]	614	1			T1	3		T16	4		T18	2
valid[2]	597	1			T1	4		T2	2		T16	9
valid[3]	640	1			T1	2		T16	4		T19	6
valid[4]	568	1			T1	2		T2	2		T16	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	49	1			T16	2		T21	1		T63	2
auto[0]	auto[0]	valid[0]	auto[1]	246	1			T1	2		T19	5		T62	4
auto[0]	auto[0]	valid[1]	auto[0]	37	1			T16	2		T18	1		T21	2
auto[0]	auto[0]	valid[1]	auto[1]	252	1			T19	4		T59	1		T62	6
auto[0]	auto[0]	valid[2]	auto[0]	40	1			T16	1		T111	1		T385	3
auto[0]	auto[0]	valid[2]	auto[1]	222	1			T1	2		T19	3		T62	3
auto[0]	auto[0]	valid[3]	auto[0]	43	1			T16	1		T63	1		T66	1
auto[0]	auto[0]	valid[3]	auto[1]	265	1			T1	1		T16	2		T19	4
auto[0]	auto[0]	valid[4]	auto[0]	41	1			T16	1		T21	1		T111	2
auto[0]	auto[0]	valid[4]	auto[1]	222	1			T1	1		T19	1		T62	4
auto[0]	auto[1]	valid[0]	auto[0]	45	1			T16	1		T21	1		T111	2
auto[0]	auto[1]	valid[0]	auto[1]	242	1			T19	4		T62	8		T116	1
auto[0]	auto[1]	valid[1]	auto[0]	42	1			T16	1		T21	1		T66	1
auto[0]	auto[1]	valid[1]	auto[1]	237	1			T1	3		T19	6		T62	3
auto[0]	auto[1]	valid[2]	auto[0]	57	1			T16	3		T63	2		T66	1
auto[0]	auto[1]	valid[2]	auto[1]	222	1			T1	2		T2	2		T16	1
auto[0]	auto[1]	valid[3]	auto[0]	55	1			T16	1		T21	2		T111	1
auto[0]	auto[1]	valid[3]	auto[1]	242	1			T1	1		T19	2		T21	2
auto[0]	auto[1]	valid[4]	auto[0]	46	1			T16	1		T21	1		T63	3
auto[0]	auto[1]	valid[4]	auto[1]	207	1			T1	1		T2	2		T19	4
auto[1]	auto[0]	valid[0]	auto[0]	41	1			T16	1		T21	1		T63	2
auto[1]	auto[0]	valid[1]	auto[0]	26	1			T16	1		T18	1		T112	1
auto[1]	auto[0]	valid[2]	auto[0]	32	1			T16	3		T67	1		T112	1
auto[1]	auto[0]	valid[3]	auto[0]	15	1			T63	1		T385	1		T380	2
auto[1]	auto[0]	valid[4]	auto[0]	28	1			T16	1		T21	3		T63	1
auto[1]	auto[1]	valid[0]	auto[0]	28	1			T16	2		T384	3		T380	1
auto[1]	auto[1]	valid[1]	auto[0]	20	1			T63	2		T111	1		T384	1
auto[1]	auto[1]	valid[2]	auto[0]	24	1			T16	1		T21	1		T111	1
auto[1]	auto[1]	valid[3]	auto[0]	20	1			T384	2		T385	3		T115	1
auto[1]	auto[1]	valid[4]	auto[0]	24	1			T111	1		T384	1		T385	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal