Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17890

1

T15

15

T16

480

T17

20

auto[1]

22975

1

T1

13

T2

23

T16

81

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34401

1

T1

13

T2

23

T15

6

auto[1]

6464

1

T15

9

T16

200

T17

12

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	21304	1			T1	13		T2	17		T15	11
others[1]	3368	1			T2	1		T15	1		T16	39
others[2]	3457	1			T2	2		T16	43		T19	51
others[3]	3780	1			T2	1		T15	1		T16	44
interest[1]	2305	1			T2	1		T16	34		T17	1
interest[4]	14035	1			T1	13		T2	12		T15	7
interest[64]	6651	1			T2	1		T15	2		T16	104

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	5861	1			T15	3		T16	142		T17	6
auto[0]	auto[0]	others[1]	958	1			T16	21		T17	1		T21	19
auto[0]	auto[0]	others[2]	961	1			T16	25		T21	26		T63	25
auto[0]	auto[0]	others[3]	1040	1			T15	1		T16	19		T17	1
auto[0]	auto[0]	interest[1]	664	1			T16	18		T21	14		T23	1
auto[0]	auto[0]	interest[4]	3848	1			T15	2		T16	94		T17	5
auto[0]	auto[0]	interest[64]	1942	1			T15	2		T16	55		T18	2
auto[0]	auto[1]	others[0]	12083	1			T1	13		T2	17		T16	40
auto[0]	auto[1]	others[1]	1879	1			T2	1		T16	6		T19	43
auto[0]	auto[1]	others[2]	1956	1			T2	2		T16	8		T19	51
auto[0]	auto[1]	others[3]	2111	1			T2	1		T16	9		T19	51
auto[0]	auto[1]	interest[1]	1288	1			T2	1		T16	4		T19	38
auto[0]	auto[1]	interest[4]	8035	1			T1	13		T2	12		T16	23
auto[0]	auto[1]	interest[64]	3658	1			T2	1		T16	14		T19	81
auto[1]	auto[0]	others[0]	3360	1			T15	8		T16	115		T17	9
auto[1]	auto[0]	others[1]	531	1			T15	1		T16	12		T17	1
auto[1]	auto[0]	others[2]	540	1			T16	10		T21	10		T63	20
auto[1]	auto[0]	others[3]	629	1			T16	16		T21	12		T63	17
auto[1]	auto[0]	interest[1]	353	1			T16	12		T17	1		T21	4
auto[1]	auto[0]	interest[4]	2152	1			T15	5		T16	75		T17	6
auto[1]	auto[0]	interest[64]	1051	1			T16	35		T17	1		T18	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal