Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	473	1			T44	11		T45	24		T46	11
all_values[1]	473	1			T44	11		T45	24		T46	11
all_values[2]	473	1			T44	11		T45	24		T46	11
all_values[3]	473	1			T44	11		T45	24		T46	11
all_values[4]	473	1			T44	11		T45	24		T46	11
all_values[5]	473	1			T44	11		T45	24		T46	11
all_values[6]	473	1			T44	11		T45	24		T46	11
all_values[7]	473	1			T44	11		T45	24		T46	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1979

1

T44

45

T45

105

T46

56

auto[1]

1805

1

T44

43

T45

87

T46

32

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1497

1

T44

33

T45

75

T46

34

auto[1]

2287

1

T44

55

T45

117

T46

54

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2187

1

T44

48

T45

105

T46

50

auto[1]

1597

1

T44

40

T45

87

T46

38

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	78	1			T44	5		T45	5		T361	3
all_values[0]	auto[0]	auto[0]	auto[1]	45	1			T45	3		T46	2		T361	1
all_values[0]	auto[0]	auto[1]	auto[0]	91	1			T44	4		T45	3		T46	3
all_values[0]	auto[0]	auto[1]	auto[1]	52	1			T45	2		T361	8		T362	1
all_values[0]	auto[1]	auto[0]	auto[1]	114	1			T44	1		T45	8		T46	5
all_values[0]	auto[1]	auto[1]	auto[1]	93	1			T44	1		T45	3		T46	1
all_values[1]	auto[0]	auto[0]	auto[0]	91	1			T44	2		T45	4		T46	2
all_values[1]	auto[0]	auto[0]	auto[1]	47	1			T44	1		T45	2		T46	2
all_values[1]	auto[0]	auto[1]	auto[0]	91	1			T44	1		T45	1		T361	3
all_values[1]	auto[0]	auto[1]	auto[1]	46	1			T44	1		T45	3		T46	2
all_values[1]	auto[1]	auto[0]	auto[1]	107	1			T44	2		T45	8		T46	5
all_values[1]	auto[1]	auto[1]	auto[1]	91	1			T44	4		T45	6		T361	2
all_values[2]	auto[0]	auto[0]	auto[0]	95	1			T45	6		T46	3		T361	4
all_values[2]	auto[0]	auto[0]	auto[1]	59	1			T44	3		T45	3		T46	1
all_values[2]	auto[0]	auto[1]	auto[0]	76	1			T45	6		T46	2		T361	1
all_values[2]	auto[0]	auto[1]	auto[1]	47	1			T44	2		T45	1		T46	2
all_values[2]	auto[1]	auto[0]	auto[1]	108	1			T44	3		T45	6		T46	2
all_values[2]	auto[1]	auto[1]	auto[1]	88	1			T44	3		T45	2		T46	1
all_values[3]	auto[0]	auto[0]	auto[0]	90	1			T44	5		T45	7		T46	2
all_values[3]	auto[0]	auto[0]	auto[1]	45	1			T45	2		T46	1		T361	3
all_values[3]	auto[0]	auto[1]	auto[0]	79	1			T44	3		T45	4		T46	1
all_values[3]	auto[0]	auto[1]	auto[1]	50	1			T45	1		T361	2		T362	1
all_values[3]	auto[1]	auto[0]	auto[1]	114	1			T44	1		T45	4		T46	5
all_values[3]	auto[1]	auto[1]	auto[1]	95	1			T44	2		T45	6		T46	2
all_values[4]	auto[0]	auto[0]	auto[0]	92	1			T44	1		T45	4		T46	3
all_values[4]	auto[0]	auto[0]	auto[1]	43	1			T45	1		T361	5		T362	2
all_values[4]	auto[0]	auto[1]	auto[0]	94	1			T44	2		T45	4		T46	3
all_values[4]	auto[0]	auto[1]	auto[1]	53	1			T44	2		T45	3		T46	1
all_values[4]	auto[1]	auto[0]	auto[1]	107	1			T44	5		T45	6		T46	4
all_values[4]	auto[1]	auto[1]	auto[1]	84	1			T44	1		T45	6		T361	3
all_values[5]	auto[0]	auto[0]	auto[0]	128	1			T44	1		T45	9		T46	7
all_values[5]	auto[0]	auto[1]	auto[0]	150	1			T44	3		T45	4		T46	2
all_values[5]	auto[1]	auto[0]	auto[1]	109	1			T44	3		T45	4		T46	1
all_values[5]	auto[1]	auto[1]	auto[1]	86	1			T44	4		T45	7		T46	1
all_values[6]	auto[0]	auto[0]	auto[0]	113	1			T44	2		T45	5		T46	2
all_values[6]	auto[0]	auto[0]	auto[1]	45	1			T44	2		T45	3		T46	1
all_values[6]	auto[0]	auto[1]	auto[0]	72	1			T44	2		T45	5		T46	2
all_values[6]	auto[0]	auto[1]	auto[1]	49	1			T45	2		T46	1		T362	5
all_values[6]	auto[1]	auto[0]	auto[1]	112	1			T44	3		T45	7		T46	3
all_values[6]	auto[1]	auto[1]	auto[1]	82	1			T44	2		T45	2		T46	2
all_values[7]	auto[0]	auto[0]	auto[0]	82	1			T44	2		T45	6		T361	3
all_values[7]	auto[0]	auto[0]	auto[1]	48	1			T44	1		T45	1		T46	3
all_values[7]	auto[0]	auto[1]	auto[0]	75	1			T45	2		T46	2		T361	1
all_values[7]	auto[0]	auto[1]	auto[1]	61	1			T44	3		T45	3		T361	4
all_values[7]	auto[1]	auto[0]	auto[1]	107	1			T44	2		T45	1		T46	2
all_values[7]	auto[1]	auto[1]	auto[1]	100	1			T44	3		T45	11		T46	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal