Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	287561	1			T1	15		T2	1		T3	1
all_values[1]	287561	1			T1	15		T2	1		T3	1
all_values[2]	287561	1			T1	15		T2	1		T3	1
all_values[3]	287561	1			T1	15		T2	1		T3	1
all_values[4]	287561	1			T1	15		T2	1		T3	1
all_values[5]	287561	1			T1	15		T2	1		T3	1
all_values[6]	287561	1			T1	15		T2	1		T3	1
all_values[7]	287561	1			T1	15		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2298087

1

T1

59

T2

8

T3

8

auto[1]

2401

1

T1

61

T22

72

T38

80

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2298364

1

T1

76

T2

8

T3

8

auto[1]

2124

1

T1

44

T8

4

T15

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	287138	1			T1	5		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	108	1			T22	4		T38	3		T39	2
all_values[0]	auto[1]	auto[0]	185	1			T1	6		T22	7		T38	7
all_values[0]	auto[1]	auto[1]	130	1			T1	4		T22	3		T38	2
all_values[1]	auto[0]	auto[0]	287147	1			T1	6		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	127	1			T1	2		T22	4		T38	4
all_values[1]	auto[1]	auto[0]	170	1			T1	7		T22	9		T38	4
all_values[1]	auto[1]	auto[1]	117	1			T22	3		T38	5		T348	3
all_values[2]	auto[0]	auto[0]	287135	1			T1	5		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	123	1			T1	3		T38	4		T39	1
all_values[2]	auto[1]	auto[0]	182	1			T1	6		T22	12		T38	2
all_values[2]	auto[1]	auto[1]	121	1			T1	1		T22	1		T38	5
all_values[3]	auto[0]	auto[0]	287127	1			T1	4		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	123	1			T1	1		T22	1		T38	4
all_values[3]	auto[1]	auto[0]	191	1			T1	4		T22	6		T38	11
all_values[3]	auto[1]	auto[1]	120	1			T1	6		T22	4		T38	3
all_values[4]	auto[0]	auto[0]	287125	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	144	1			T1	3		T22	2		T38	5
all_values[4]	auto[1]	auto[0]	164	1			T1	3		T22	7		T38	4
all_values[4]	auto[1]	auto[1]	128	1			T1	8		T22	4		T38	5
all_values[5]	auto[0]	auto[0]	286935	1			T1	8		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	326	1			T1	1		T8	4		T15	2
all_values[5]	auto[1]	auto[0]	192	1			T1	3		T22	2		T38	9
all_values[5]	auto[1]	auto[1]	108	1			T1	3		T22	6		T38	3
all_values[6]	auto[0]	auto[0]	287158	1			T1	7		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	100	1			T1	4		T22	10		T38	1
all_values[6]	auto[1]	auto[0]	203	1			T1	2		T38	14		T39	5
all_values[6]	auto[1]	auto[1]	100	1			T1	2		T22	3		T348	4
all_values[7]	auto[0]	auto[0]	287137	1			T1	4		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	134	1			T1	5		T22	5		T38	5
all_values[7]	auto[1]	auto[0]	175	1			T1	5		T22	4		T38	3
all_values[7]	auto[1]	auto[1]	115	1			T1	1		T22	1		T38	3