Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
71.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	34	50	59.52

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	29	19	39.58	100	1	1	0
cr_modeXdummyXnum_lanes	36	5	31	86.11	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	1100	1			T7	24		T9	2		T11	2
auto[SpiFlashAddrCfg]	908	1			T6	20		T10	2		T11	6
auto[SpiFlashAddr3b]	1033	1			T10	4		T11	2		T13	10
auto[SpiFlashAddr4b]	812	1			T5	4		T10	2		T11	8

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3013

1

T7

24

T5

4

T9

2

auto[1]

840

1

T10

8

T74

2

T75

18

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1953

1

T7

20

T5

4

T9

2

auto[1]

1900

1

T7

4

T6

12

T10

4

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1486	1			T7	24		T9	2		T6	6
values[1]	72	1			T10	2		T75	4		T101	10
values[2]	149	1			T11	2		T55	4		T58	4
values[3]	241	1			T13	2		T69	2		T72	8
values[4]	207	1			T69	5		T44	2		T26	6
values[5]	155	1			T6	6		T10	4		T58	2
values[6]	180	1			T13	2		T68	6		T101	4
values[7]	200	1			T13	2		T82	2		T45	6
values[8]	1163	1			T5	4		T6	8		T10	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3370

1

T7

24

T5

4

T9

2

auto[1]

483

1

T69

7

T65

19

T284

15

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3761

1

T7

24

T5

4

T9

2

write

92

1

T11

6

T72

4

T73

6

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1844

1

T5

2

T9

2

T6

14

valids[0x1]

2009

1

T7

24

T5

2

T6

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	176	1			T7	2		T11	2		T42	4
internal_process_ops[0x5a]	156	1			T43	2		T45	4		T101	10
internal_process_ops[0x05]	200	1			T7	12		T82	4		T43	2
internal_process_ops[0x35]	186	1			T7	2		T42	2		T43	4
internal_process_ops[0x15]	182	1			T7	8		T68	2		T75	2
internal_process_ops[0x03]	289	1			T6	6		T10	2		T179	4
internal_process_ops[0x0b]	266	1			T42	2		T179	8		T55	2
internal_process_ops[0x3b]	313	1			T6	6		T68	4		T69	2
internal_process_ops[0x6b]	307	1			T6	8		T13	2		T75	2
internal_process_ops[0xbb]	259	1			T10	2		T68	2		T82	6
internal_process_ops[0xeb]	219	1			T5	2		T11	2		T13	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3817

1

T7

24

T5

4

T9

2

auto[1]

36

1

T76

2

T77

4

T78

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3853

1

T7

24

T5

4

T9

2

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	29	19	39.58	29
Automatically Generated Cross Bins	48	29	19	39.58	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[read]	[auto[SpiFlashAddrDisabled]]	*	[auto[0]]	--	--	2
[auto[1]]	[write]	*	*	*	--	--	16

Uncovered bins

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[read]	[auto[SpiFlashAddrCfg] , auto[SpiFlashAddr3b] , auto[SpiFlashAddr4b]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

860

1

T7

24

T9

2

T11

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

218

1

T75

6

T179

2

T77

18

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

548

1

T6

20

T11

6

T13

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

152

1

T10

2

T75

2

T101

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

608

1

T11

2

T13

10

T68

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

274

1

T10

4

T74

2

T75

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

458

1

T5

4

T11

2

T13

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

160

1

T10

2

T75

8

T179

10

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10

1

T199

2

T251

4

T190

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

12

1

T77

4

T86

2

T191

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

14

1

T254

2

T215

2

T186

6

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

10

1

T78

2

T79

2

T88

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

6

1

T262

2

T285

2

T203

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

8

1

T76

2

T84

2

T85

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

26

1

T11

6

T72

4

T73

6

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

6

1

T83

6

-

-

-

-

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

184

1

T69

2

T65

3

T284

8

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

137

1

T69

5

T65

12

T284

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

162

1

T65

4

T284

2

T66

6

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	5	31	86.11	5

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[0] , values[1]]	[valids[0x0]]	--	--	2
[auto[1]]	[values[4]]	[valids[0x1]]	0	1	1
[auto[1]]	[values[6]]	[valids[0x1]]	0	1	1

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	306	1			T9	2		T11	2		T75	8
auto[0]	values[0]	valids[0x1]	1128	1			T7	24		T6	6		T11	12
auto[0]	values[1]	valids[0x1]	70	1			T10	2		T75	4		T101	10
auto[0]	values[2]	valids[0x0]	86	1			T11	2		T55	4		T27	4
auto[0]	values[2]	valids[0x1]	24	1			T58	4		T177	2		T226	2
auto[0]	values[3]	valids[0x0]	110	1			T13	2		T120	4		T121	4
auto[0]	values[3]	valids[0x1]	76	1			T72	8		T92	4		T199	2
auto[0]	values[4]	valids[0x0]	120	1			T26	6		T169	4		T76	2
auto[0]	values[4]	valids[0x1]	46	1			T44	2		T121	4		T95	2
auto[0]	values[5]	valids[0x0]	88	1			T6	6		T10	2		T58	2
auto[0]	values[5]	valids[0x1]	50	1			T10	2		T220	4		T178	4
auto[0]	values[6]	valids[0x0]	104	1			T13	2		T68	6		T101	4
auto[0]	values[6]	valids[0x1]	58	1			T77	2		T225	2		T286	6
auto[0]	values[7]	valids[0x0]	92	1			T82	2		T72	2		T26	2
auto[0]	values[7]	valids[0x1]	52	1			T13	2		T45	6		T101	6
auto[0]	values[8]	valids[0x0]	636	1			T5	2		T6	8		T10	2
auto[0]	values[8]	valids[0x1]	324	1			T5	2		T13	2		T179	10
auto[1]	values[0]	valids[0x1]	52	1			T284	5		T66	6		T67	2
auto[1]	values[1]	valids[0x1]	2	1			T287	2		-	-		-	-
auto[1]	values[2]	valids[0x0]	37	1			T67	3		T288	2		T289	3
auto[1]	values[2]	valids[0x1]	2	1			T290	2		-	-		-	-
auto[1]	values[3]	valids[0x0]	39	1			T69	2		T66	3		T67	10
auto[1]	values[3]	valids[0x1]	16	1			T65	3		T288	3		T291	3
auto[1]	values[4]	valids[0x0]	41	1			T69	5		T284	7		T96	3
auto[1]	values[5]	valids[0x0]	6	1			T289	6		-	-		-	-
auto[1]	values[5]	valids[0x1]	11	1			T96	4		T292	3		T293	4
auto[1]	values[6]	valids[0x0]	18	1			T294	4		T291	2		T295	3
auto[1]	values[7]	valids[0x0]	43	1			T65	5		T287	5		T296	7
auto[1]	values[7]	valids[0x1]	13	1			T297	8		T298	5		-	-
auto[1]	values[8]	valids[0x0]	118	1			T65	6		T66	6		T96	3
auto[1]	values[8]	valids[0x1]	85	1			T65	5		T284	3		T96	5