Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
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Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1915865 1 T7 25004 T5 1 T9 406


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1756737 1 T7 25004 T5 1 T9 406
auto[1] 159128 1 T43 10626 T44 416 T58 512


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 488339 1 T7 3349 T5 1 T9 327
auto[524288:1048575] 216092 1 T7 5227 T69 13158 T42 908
auto[1048576:1572863] 232793 1 T7 667 T6 19025 T69 11407
auto[1572864:2097151] 213609 1 T7 344 T6 2407 T69 11402
auto[2097152:2621439] 161740 1 T7 6010 T9 53 T6 515
auto[2621440:3145727] 240459 1 T7 2985 T6 896 T69 10939
auto[3145728:3670015] 199685 1 T7 1999 T6 10262 T69 3008
auto[3670016:4194303] 163148 1 T7 4423 T9 26 T6 25


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 171330 1 T7 66 T5 1 T9 30
auto[1] 1744535 1 T7 24938 T9 376 T6 66702


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1915865 1 T7 25004 T5 1 T9 406


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 360909 1 T7 3349 T5 1 T9 327
auto[0] auto[0] auto[0:524287] auto[1] 127430 1 T43 10626 T44 185 T58 512
auto[0] auto[0] auto[524288:1048575] auto[0] 205954 1 T7 5227 T69 13158 T42 908
auto[0] auto[0] auto[524288:1048575] auto[1] 10138 1 T99 254 T169 6 T170 1
auto[0] auto[0] auto[1048576:1572863] auto[0] 228038 1 T7 667 T6 19025 T69 11407
auto[0] auto[0] auto[1048576:1572863] auto[1] 4755 1 T44 22 T121 2 T99 16
auto[0] auto[0] auto[1572864:2097151] auto[0] 212179 1 T7 344 T6 2407 T69 11402
auto[0] auto[0] auto[1572864:2097151] auto[1] 1430 1 T171 1394 T46 13 T172 8
auto[0] auto[0] auto[2097152:2621439] auto[0] 160555 1 T7 6010 T9 53 T6 515
auto[0] auto[0] auto[2097152:2621439] auto[1] 1185 1 T171 3 T99 138 T169 254
auto[0] auto[0] auto[2621440:3145727] auto[0] 232550 1 T7 2985 T6 896 T69 10939
auto[0] auto[0] auto[2621440:3145727] auto[1] 7909 1 T44 209 T121 511 T171 2250
auto[0] auto[0] auto[3145728:3670015] auto[0] 195899 1 T7 1999 T6 10262 T69 3008
auto[0] auto[0] auto[3145728:3670015] auto[1] 3786 1 T171 1986 T99 497 T173 256
auto[0] auto[0] auto[3670016:4194303] auto[0] 160653 1 T7 4423 T9 26 T6 25
auto[0] auto[0] auto[3670016:4194303] auto[1] 2495 1 T171 918 T99 3 T169 256


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 171330 1 T7 66 T5 1 T9 30
auto[0] auto[0] auto[1] 1744535 1 T7 24938 T9 376 T6 66702

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