Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
73.97	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	38	90	70.31

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	38	90	70.31	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2530

1

T7

24

T5

4

T9

2

auto[1]

840

1

T10

8

T74

2

T75

18

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	384	1			T7	24		T5	4		T11	18
values[1]	402	1			T9	2		T82	24		T286	28
values[2]	296	1			T75	18		T158	2		T45	10
values[3]	566	1			T10	8		T13	16		T74	2
values[4]	472	1			T6	20		T101	34		T121	20
values[5]	332	1			T44	4		T55	22		T26	28
values[6]	438	1			T179	22		T58	14		T120	6
values[7]	480	1			T42	8		T72	28		T176	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	516	1			T55	22		T92	22		T177	6
values[1]	410	1			T10	8		T68	12		T75	18
values[2]	398	1			T5	4		T9	2		T11	18
values[3]	434	1			T13	16		T158	2		T53	2
values[4]	598	1			T74	2		T58	14		T72	28
values[5]	212	1			T43	14		T171	14		T237	2
values[6]	478	1			T42	8		T101	34		T120	6
values[7]	324	1			T7	24		T6	20		T207	22

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	38	90	70.31	38

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[values[6]]	0	1	1
[auto[0]]	[values[1]]	[values[0]]	0	1	1
[auto[0]]	[values[5]]	[values[1]]	0	1	1
[auto[0]]	[values[5]]	[values[7]]	0	1	1
[auto[0]]	[values[6]]	[values[2]]	0	1	1
[auto[0]]	[values[6]]	[values[5]]	0	1	1
[auto[0]]	[values[7]]	[values[0]]	0	1	1
[auto[1]]	[values[0]]	[values[0]]	0	1	1
[auto[1]]	[values[0]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[0]]	[values[5]]	0	1	1
[auto[1]]	[values[0]]	[values[7]]	0	1	1
[auto[1]]	[values[1]]	[values[2]]	0	1	1
[auto[1]]	[values[1]]	[values[5]]	0	1	1
[auto[1]]	[values[1]]	[values[7]]	0	1	1
[auto[1]]	[values[2]]	[values[0]]	0	1	1
[auto[1]]	[values[2]]	[values[2]]	0	1	1
[auto[1]]	[values[2]]	[values[5]]	0	1	1
[auto[1]]	[values[2]]	[values[7]]	0	1	1
[auto[1]]	[values[3]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[3]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[4]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[4]]	[values[4]]	0	1	1
[auto[1]]	[values[4]]	[values[7]]	0	1	1
[auto[1]]	[values[5]]	[values[0]]	0	1	1
[auto[1]]	[values[5]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[5]]	[values[5] , values[6]]	--	--	2
[auto[1]]	[values[6]]	[values[3]]	0	1	1
[auto[1]]	[values[6]]	[values[6]]	0	1	1
[auto[1]]	[values[7]]	[values[0]]	0	1	1
[auto[1]]	[values[7]]	[values[7]]	0	1	1

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	26	1			T81	26		-	-		-	-
auto[0]	values[0]	values[1]	68	1			T68	12		T213	10		T299	8
auto[0]	values[0]	values[2]	38	1			T5	4		T11	18		T259	16
auto[0]	values[0]	values[3]	16	1			T53	2		T300	6		T254	4
auto[0]	values[0]	values[4]	58	1			T223	6		T301	22		T302	30
auto[0]	values[0]	values[5]	62	1			T43	14		T209	10		T275	18
auto[0]	values[0]	values[7]	72	1			T7	24		T190	18		T282	30
auto[0]	values[1]	values[1]	46	1			T116	4		T303	14		T304	28
auto[0]	values[1]	values[2]	130	1			T9	2		T82	24		T25	4
auto[0]	values[1]	values[3]	22	1			T234	2		T256	20		-	-
auto[0]	values[1]	values[4]	26	1			T305	20		T306	6		-	-
auto[0]	values[1]	values[5]	26	1			T240	8		T307	10		T308	8
auto[0]	values[1]	values[6]	22	1			T280	22		-	-		-	-
auto[0]	values[1]	values[7]	50	1			T249	2		T219	16		T257	32
auto[0]	values[2]	values[0]	22	1			T309	2		T115	20		-	-
auto[0]	values[2]	values[1]	8	1			T100	8		-	-		-	-
auto[0]	values[2]	values[2]	4	1			T310	4		-	-		-	-
auto[0]	values[2]	values[3]	48	1			T158	2		T45	10		T228	24
auto[0]	values[2]	values[4]	22	1			T169	12		T95	8		T311	2
auto[0]	values[2]	values[5]	4	1			T312	4		-	-		-	-
auto[0]	values[2]	values[6]	24	1			T29	18		T313	6		-	-
auto[0]	values[2]	values[7]	16	1			T314	6		T315	10		-	-
auto[0]	values[3]	values[0]	74	1			T92	22		T251	16		T175	18
auto[0]	values[3]	values[1]	54	1			T23	4		T245	2		T316	6
auto[0]	values[3]	values[2]	48	1			T99	18		T278	30		-	-
auto[0]	values[3]	values[3]	66	1			T13	16		T204	14		T317	34
auto[0]	values[3]	values[4]	44	1			T253	14		T188	30		-	-
auto[0]	values[3]	values[5]	34	1			T255	10		T318	24		-	-
auto[0]	values[3]	values[6]	84	1			T89	10		T173	2		T244	8
auto[0]	values[3]	values[7]	56	1			T319	16		T211	32		T320	8
auto[0]	values[4]	values[0]	70	1			T177	6		T233	18		T321	6
auto[0]	values[4]	values[1]	34	1			T170	14		T322	20		-	-
auto[0]	values[4]	values[2]	94	1			T121	20		T27	28		T273	14
auto[0]	values[4]	values[3]	18	1			T197	2		T285	16		-	-
auto[0]	values[4]	values[4]	16	1			T172	14		T323	2		-	-
auto[0]	values[4]	values[5]	20	1			T324	4		T270	2		T183	14
auto[0]	values[4]	values[6]	92	1			T28	30		T196	14		T193	22
auto[0]	values[4]	values[7]	36	1			T6	20		T221	14		T98	2
auto[0]	values[5]	values[0]	96	1			T55	22		T225	14		T192	24
auto[0]	values[5]	values[2]	44	1			T44	4		T263	2		T266	26
auto[0]	values[5]	values[3]	30	1			T26	28		T281	2		-	-
auto[0]	values[5]	values[4]	32	1			T220	26		T230	4		T325	2
auto[0]	values[5]	values[5]	10	1			T232	4		T238	6		-	-
auto[0]	values[5]	values[6]	10	1			T239	2		T326	6		T243	2
auto[0]	values[6]	values[0]	110	1			T80	28		T327	16		T181	26
auto[0]	values[6]	values[1]	22	1			T46	12		T328	10		-	-
auto[0]	values[6]	values[3]	32	1			T184	2		T329	30		-	-
auto[0]	values[6]	values[4]	54	1			T58	14		T208	16		T47	12
auto[0]	values[6]	values[6]	78	1			T120	6		T189	26		T186	28
auto[0]	values[6]	values[7]	24	1			T261	8		T330	16		-	-
auto[0]	values[7]	values[1]	44	1			T274	14		T331	30		-	-
auto[0]	values[7]	values[2]	20	1			T199	10		T24	10		-	-
auto[0]	values[7]	values[3]	70	1			T176	8		T178	34		T332	28
auto[0]	values[7]	values[4]	110	1			T72	28		T73	28		T242	30
auto[0]	values[7]	values[5]	40	1			T171	14		T187	6		T229	8
auto[0]	values[7]	values[6]	44	1			T42	8		T174	14		T231	16
auto[0]	values[7]	values[7]	10	1			T269	10		-	-		-	-
auto[1]	values[0]	values[1]	10	1			T76	10		-	-		-	-
auto[1]	values[0]	values[4]	10	1			T333	10		-	-		-	-
auto[1]	values[0]	values[6]	24	1			T334	24		-	-		-	-
auto[1]	values[1]	values[0]	10	1			T191	10		-	-		-	-
auto[1]	values[1]	values[1]	2	1			T258	2		-	-		-	-
auto[1]	values[1]	values[3]	2	1			T210	2		-	-		-	-
auto[1]	values[1]	values[4]	38	1			T335	14		T241	24		-	-
auto[1]	values[1]	values[6]	28	1			T286	28		-	-		-	-
auto[1]	values[2]	values[1]	42	1			T75	18		T336	4		T87	20
auto[1]	values[2]	values[3]	66	1			T265	14		T79	30		T224	22
auto[1]	values[2]	values[4]	28	1			T252	28		-	-		-	-
auto[1]	values[2]	values[6]	12	1			T217	12		-	-		-	-
auto[1]	values[3]	values[0]	88	1			T195	32		T182	36		T272	20
auto[1]	values[3]	values[1]	8	1			T10	8		-	-		-	-
auto[1]	values[3]	values[4]	10	1			T74	2		T337	8		-	-
auto[1]	values[4]	values[3]	46	1			T338	30		T339	16		-	-
auto[1]	values[4]	values[5]	12	1			T88	12		-	-		-	-
auto[1]	values[4]	values[6]	34	1			T101	34		-	-		-	-
auto[1]	values[5]	values[1]	12	1			T84	12		-	-		-	-
auto[1]	values[5]	values[4]	50	1			T83	32		T222	18		-	-
auto[1]	values[5]	values[7]	48	1			T207	22		T235	26		-	-
auto[1]	values[6]	values[0]	20	1			T200	10		T340	10		-	-
auto[1]	values[6]	values[1]	24	1			T179	22		T341	2		-	-
auto[1]	values[6]	values[2]	10	1			T86	10		-	-		-	-
auto[1]	values[6]	values[4]	50	1			T226	6		T194	34		T277	10
auto[1]	values[6]	values[5]	2	1			T237	2		-	-		-	-
auto[1]	values[6]	values[7]	12	1			T342	12		-	-		-	-
auto[1]	values[7]	values[1]	36	1			T206	14		T343	22		-	-
auto[1]	values[7]	values[2]	10	1			T246	10		-	-		-	-
auto[1]	values[7]	values[3]	18	1			T78	18		-	-		-	-
auto[1]	values[7]	values[4]	50	1			T85	24		T201	26		-	-
auto[1]	values[7]	values[5]	2	1			T260	2		-	-		-	-
auto[1]	values[7]	values[6]	26	1			T77	26		-	-		-	-