Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.52	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	4	56	93.33

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	4	56	93.33	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	104	1			T6	2		T45	2		T169	6
auto[ReadAddrCrossIntoMailbox]	34	1			T6	4		T120	2		T213	4
auto[ReadAddrCrossOutOfMailbox]	46	1			T6	4		T213	2		T244	2
auto[ReadAddrCrossAllMailbox]	44	1			T6	6		T213	2		T231	2
auto[ReadAddrOutsideMailbox]	918	1			T5	2		T6	4		T10	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

573

1

T5

1

T6

10

T10

2

auto[1]

573

1

T5

1

T6

10

T10

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	196	1			T6	6		T10	2		T179	4
read_ops[0x0b]	172	1			T42	2		T179	8		T55	2
read_ops[0x3b]	196	1			T6	6		T68	4		T55	8
read_ops[0x6b]	236	1			T6	8		T13	2		T75	2
read_ops[0xbb]	186	1			T10	2		T68	2		T82	6
read_ops[0xeb]	160	1			T5	2		T11	2		T13	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	4	56	93.33	4

Automatically Generated Cross Bins for cr_all

Element holes

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	NUMBER	STATUS
[read_ops[0x3b]]	[auto[ReadAddrCrossIntoMailbox]]	*	--	--	2
[read_ops[0xbb]]	[auto[ReadAddrCrossAllMailbox]]	*	--	--	2

Covered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	14	1			T6	1		T45	1		T208	3
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	14	1			T6	1		T45	1		T208	3
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T344	2		T267	1		-	-
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T344	2		T267	1		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T244	1		T301	1		T344	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T244	1		T301	1		T344	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T6	2		T267	1		T303	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T6	2		T267	1		T303	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	72	1			T10	1		T179	2		T82	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	72	1			T10	1		T179	2		T82	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	6	1			T225	1		T170	1		T209	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	6	1			T225	1		T170	1		T209	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T213	2		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T213	2		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T213	1		T301	1		T267	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T213	1		T301	1		T267	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T213	1		T301	2		T345	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T213	1		T301	2		T345	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	69	1			T42	1		T179	4		T55	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	69	1			T42	1		T179	4		T55	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	9	1			T169	1		T232	1		T225	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	9	1			T169	1		T232	1		T225	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	7	1			T6	2		T346	1		T247	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	7	1			T6	2		T346	1		T247	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T6	1		T267	1		T247	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T6	1		T267	1		T247	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	79	1			T68	2		T55	4		T58	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	79	1			T68	2		T55	4		T58	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	8	1			T169	2		T269	1		T248	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	8	1			T169	2		T269	1		T248	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	5	1			T6	2		T120	1		T267	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	5	1			T6	2		T120	1		T267	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T267	1		T303	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T267	1		T303	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	5	1			T301	1		T267	3		T247	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	5	1			T301	1		T267	3		T247	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	98	1			T6	2		T13	1		T75	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	98	1			T6	2		T13	1		T75	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	8	1			T208	1		T170	1		T209	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	8	1			T208	1		T170	1		T209	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T244	1		T247	1		T303	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T244	1		T247	1		T303	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T247	1		T303	1		T318	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T247	1		T303	1		T318	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	79	1			T10	1		T68	1		T82	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	79	1			T10	1		T68	1		T82	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	7	1			T244	1		T269	4		T236	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	7	1			T244	1		T269	4		T236	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	4	1			T324	2		T318	2		-	-
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	4	1			T324	2		T318	2		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T318	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T318	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	6	1			T231	1		T301	1		T267	3
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	6	1			T231	1		T301	1		T267	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	62	1			T5	1		T11	1		T13	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	62	1			T5	1		T11	1		T13	1