Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	287561	1			T1	15		T2	1		T3	1
all_pins[1]	287561	1			T1	15		T2	1		T3	1
all_pins[2]	287561	1			T1	15		T2	1		T3	1
all_pins[3]	287561	1			T1	15		T2	1		T3	1
all_pins[4]	287561	1			T1	15		T2	1		T3	1
all_pins[5]	287561	1			T1	15		T2	1		T3	1
all_pins[6]	287561	1			T1	15		T2	1		T3	1
all_pins[7]	287561	1			T1	15		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2299549	1			T1	95		T2	8		T3	8
values[0x1]	939	1			T1	25		T22	25		T38	26
transitions[0x0=>0x1]	714	1			T1	18		T22	19		T38	21
transitions[0x1=>0x0]	723	1			T1	18		T22	19		T38	21

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	287431	1			T1	11		T2	1		T3	1
all_pins[0]	values[0x1]	130	1			T1	4		T22	3		T38	2
all_pins[0]	transitions[0x0=>0x1]	100	1			T1	4		T22	3		T38	2
all_pins[0]	transitions[0x1=>0x0]	87	1			T22	3		T38	5		T348	3
all_pins[1]	values[0x0]	287444	1			T1	15		T2	1		T3	1
all_pins[1]	values[0x1]	117	1			T22	3		T38	5		T348	3
all_pins[1]	transitions[0x0=>0x1]	93	1			T22	3		T38	4		T348	1
all_pins[1]	transitions[0x1=>0x0]	97	1			T1	1		T22	1		T38	4
all_pins[2]	values[0x0]	287440	1			T1	14		T2	1		T3	1
all_pins[2]	values[0x1]	121	1			T1	1		T22	1		T38	5
all_pins[2]	transitions[0x0=>0x1]	85	1			T1	1		T22	1		T38	3
all_pins[2]	transitions[0x1=>0x0]	84	1			T1	6		T22	4		T38	1
all_pins[3]	values[0x0]	287441	1			T1	9		T2	1		T3	1
all_pins[3]	values[0x1]	120	1			T1	6		T22	4		T38	3
all_pins[3]	transitions[0x0=>0x1]	92	1			T1	2		T22	2		T38	2
all_pins[3]	transitions[0x1=>0x0]	100	1			T1	4		T22	2		T38	4
all_pins[4]	values[0x0]	287433	1			T1	7		T2	1		T3	1
all_pins[4]	values[0x1]	128	1			T1	8		T22	4		T38	5
all_pins[4]	transitions[0x0=>0x1]	110	1			T1	6		T22	3		T38	4
all_pins[4]	transitions[0x1=>0x0]	90	1			T1	1		T22	5		T38	2
all_pins[5]	values[0x0]	287453	1			T1	12		T2	1		T3	1
all_pins[5]	values[0x1]	108	1			T1	3		T22	6		T38	3
all_pins[5]	transitions[0x0=>0x1]	79	1			T1	2		T22	3		T38	3
all_pins[5]	transitions[0x1=>0x0]	71	1			T1	1		T348	2		T347	2
all_pins[6]	values[0x0]	287461	1			T1	13		T2	1		T3	1
all_pins[6]	values[0x1]	100	1			T1	2		T22	3		T348	4
all_pins[6]	transitions[0x0=>0x1]	77	1			T1	2		T22	3		T348	3
all_pins[6]	transitions[0x1=>0x0]	92	1			T1	1		T22	1		T38	3
all_pins[7]	values[0x0]	287446	1			T1	14		T2	1		T3	1
all_pins[7]	values[0x1]	115	1			T1	1		T22	1		T38	3
all_pins[7]	transitions[0x0=>0x1]	78	1			T1	1		T22	1		T38	3
all_pins[7]	transitions[0x1=>0x0]	102	1			T1	4		T22	3		T38	2