Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
62.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	55	73	57.03

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	55	73	57.03	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	466	1			T174	14		T78	18		T175	18
values[1]	510	1			T6	20		T11	18		T68	12
values[2]	370	1			T74	2		T73	28		T27	28
values[3]	552	1			T158	2		T82	24		T99	18
values[4]	310	1			T75	18		T169	12		T89	10
values[5]	376	1			T9	2		T13	16		T44	4
values[6]	430	1			T7	24		T10	8		T176	8
values[7]	356	1			T5	4		T43	14		T101	34

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	256	1			T74	2		T120	6		T177	6
values[1]	328	1			T42	8		T53	2		T121	20
values[2]	542	1			T11	18		T82	24		T92	22
values[3]	434	1			T158	2		T44	4		T73	28
values[4]	530	1			T43	14		T101	34		T176	8
values[5]	466	1			T13	16		T72	28		T178	34
values[6]	356	1			T7	24		T5	4		T9	2
values[7]	458	1			T75	18		T179	22		T55	22

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3334

1

T7

24

T5

4

T9

2

auto[1]

36

1

T76

2

T77

4

T78

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	55	73	57.03	55

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[2]]	*	--	--	8
[auto[1]]	[values[4]]	*	--	--	8
[auto[1]]	[values[6] , values[7]]	*	--	--	16

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[2]]	[values[1]]	0	1	1
[auto[0]]	[values[4]]	[values[4]]	0	1	1
[auto[1]]	[values[0]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[0]]	[values[4]]	0	1	1
[auto[1]]	[values[0]]	[values[7]]	0	1	1
[auto[1]]	[values[1]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[1]]	[values[7]]	0	1	1
[auto[1]]	[values[3]]	[values[0] , values[1] , values[2] , values[3] , values[4] , values[5]]	--	--	6
[auto[1]]	[values[3]]	[values[7]]	0	1	1
[auto[1]]	[values[5]]	[values[2] , values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	6

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	46	1			T175	18		T180	2		T181	26
auto[0]	values[0]	values[1]	80	1			T182	36		T183	14		T184	2
auto[0]	values[0]	values[2]	58	1			T87	18		T185	12		T186	28
auto[0]	values[0]	values[3]	32	1			T85	22		T88	10		-	-
auto[0]	values[0]	values[4]	138	1			T187	6		T188	30		T189	26
auto[0]	values[0]	values[5]	22	1			T190	18		T191	4		-	-
auto[0]	values[0]	values[6]	54	1			T174	14		T78	16		T192	24
auto[0]	values[0]	values[7]	22	1			T193	22		-	-		-	-
auto[0]	values[1]	values[0]	40	1			T120	6		T194	34		-	-
auto[0]	values[1]	values[1]	8	1			T42	8		-	-		-	-
auto[0]	values[1]	values[2]	70	1			T11	18		T195	32		T196	14
auto[0]	values[1]	values[3]	28	1			T197	2		T86	8		T198	18
auto[0]	values[1]	values[4]	126	1			T199	10		T79	28		T200	10
auto[0]	values[1]	values[5]	38	1			T72	28		T84	10		-	-
auto[0]	values[1]	values[6]	132	1			T6	20		T68	12		T58	14
auto[0]	values[1]	values[7]	58	1			T179	22		T201	26		T202	10
auto[0]	values[2]	values[0]	22	1			T74	2		T203	20		-	-
auto[0]	values[2]	values[2]	66	1			T204	14		T205	14		T206	14
auto[0]	values[2]	values[3]	90	1			T73	28		T27	28		T207	22
auto[0]	values[2]	values[4]	54	1			T208	16		T209	10		T210	2
auto[0]	values[2]	values[5]	50	1			T211	32		T212	18		-	-
auto[0]	values[2]	values[6]	34	1			T213	10		T214	12		T215	4
auto[0]	values[2]	values[7]	54	1			T171	14		T46	12		T23	4
auto[0]	values[3]	values[0]	22	1			T216	22		-	-		-	-
auto[0]	values[3]	values[1]	48	1			T217	12		T218	20		T219	16
auto[0]	values[3]	values[2]	174	1			T82	24		T92	22		T220	26
auto[0]	values[3]	values[3]	74	1			T158	2		T99	18		T24	10
auto[0]	values[3]	values[4]	32	1			T221	14		T222	18		-	-
auto[0]	values[3]	values[5]	40	1			T223	6		T47	12		T224	22
auto[0]	values[3]	values[6]	8	1			T76	8		-	-		-	-
auto[0]	values[3]	values[7]	152	1			T225	14		T226	6		T80	28
auto[0]	values[4]	values[0]	6	1			T227	6		-	-		-	-
auto[0]	values[4]	values[1]	32	1			T228	24		T229	8		-	-
auto[0]	values[4]	values[2]	62	1			T230	4		T231	16		T116	4
auto[0]	values[4]	values[3]	46	1			T232	4		T233	18		T234	2
auto[0]	values[4]	values[5]	78	1			T178	34		T235	26		T236	18
auto[0]	values[4]	values[6]	28	1			T169	12		T237	2		T238	6
auto[0]	values[4]	values[7]	58	1			T75	18		T89	10		T239	2
auto[0]	values[5]	values[0]	28	1			T240	8		T241	20		-	-
auto[0]	values[5]	values[1]	90	1			T53	2		T121	20		T242	30
auto[0]	values[5]	values[2]	16	1			T170	14		T243	2		-	-
auto[0]	values[5]	values[3]	30	1			T44	4		T244	8		T245	2
auto[0]	values[5]	values[4]	32	1			T246	10		T247	22		-	-
auto[0]	values[5]	values[5]	106	1			T13	16		T28	30		T248	14
auto[0]	values[5]	values[6]	16	1			T9	2		T45	10		T249	2
auto[0]	values[5]	values[7]	48	1			T55	22		T25	4		T250	6
auto[0]	values[6]	values[0]	58	1			T251	16		T252	28		T253	14
auto[0]	values[6]	values[1]	62	1			T254	4		T255	10		T256	20
auto[0]	values[6]	values[2]	50	1			T257	32		T258	2		T259	16
auto[0]	values[6]	values[3]	74	1			T260	2		T261	8		T262	22
auto[0]	values[6]	values[4]	44	1			T176	8		T263	2		T264	24
auto[0]	values[6]	values[5]	58	1			T265	14		T29	18		T266	26
auto[0]	values[6]	values[6]	70	1			T7	24		T10	8		T267	38
auto[0]	values[6]	values[7]	14	1			T98	2		T268	12		-	-
auto[0]	values[7]	values[0]	30	1			T177	6		T173	2		T269	10
auto[0]	values[7]	values[1]	2	1			T270	2		-	-		-	-
auto[0]	values[7]	values[2]	44	1			T271	10		T272	20		T273	14
auto[0]	values[7]	values[3]	54	1			T274	14		T275	18		T276	22
auto[0]	values[7]	values[4]	102	1			T43	14		T101	34		T277	10
auto[0]	values[7]	values[5]	66	1			T278	30		T279	12		T280	22
auto[0]	values[7]	values[6]	6	1			T5	4		T281	2		-	-
auto[0]	values[7]	values[7]	52	1			T115	20		T282	30		T283	2
auto[1]	values[0]	values[2]	2	1			T87	2		-	-		-	-
auto[1]	values[0]	values[3]	4	1			T85	2		T88	2		-	-
auto[1]	values[0]	values[5]	6	1			T191	6		-	-		-	-
auto[1]	values[0]	values[6]	2	1			T78	2		-	-		-	-
auto[1]	values[1]	values[3]	2	1			T86	2		-	-		-	-
auto[1]	values[1]	values[4]	2	1			T79	2		-	-		-	-
auto[1]	values[1]	values[5]	2	1			T84	2		-	-		-	-
auto[1]	values[1]	values[6]	4	1			T77	4		-	-		-	-
auto[1]	values[3]	values[6]	2	1			T76	2		-	-		-	-
auto[1]	values[5]	values[0]	4	1			T241	4		-	-		-	-
auto[1]	values[5]	values[1]	6	1			T83	6		-	-		-	-