Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1575

1

T16

8

T17

18

T18

16

auto[1]

1498

1

T16

15

T17

8

T18

10

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

788

1

T18

26

T19

1

T61

10

auto[1]

2285

1

T16

23

T17

26

T20

60

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2765

1

T16

23

T17

26

T18

15

auto[1]

308

1

T18

11

T19

1

T61

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	607	1			T16	5		T17	6		T18	2
valid[1]	584	1			T16	2		T17	4		T18	7
valid[2]	599	1			T16	5		T17	4		T18	9
valid[3]	619	1			T16	8		T17	7		T18	4
valid[4]	664	1			T16	3		T17	5		T18	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	56	1			T18	1		T63	2		T64	1
auto[0]	auto[0]	valid[0]	auto[1]	223	1			T16	3		T17	5		T20	2
auto[0]	auto[0]	valid[1]	auto[0]	60	1			T18	4		T63	1		T403	1
auto[0]	auto[0]	valid[1]	auto[1]	201	1			T17	1		T20	6		T109	9
auto[0]	auto[0]	valid[2]	auto[0]	43	1			T18	3		T64	1		T70	2
auto[0]	auto[0]	valid[2]	auto[1]	233	1			T16	2		T17	1		T20	5
auto[0]	auto[0]	valid[3]	auto[0]	56	1			T18	1		T61	2		T63	1
auto[0]	auto[0]	valid[3]	auto[1]	242	1			T16	2		T17	7		T20	7
auto[0]	auto[0]	valid[4]	auto[0]	60	1			T18	2		T61	1		T63	1
auto[0]	auto[0]	valid[4]	auto[1]	238	1			T16	1		T17	4		T20	10
auto[0]	auto[1]	valid[0]	auto[0]	47	1			T61	1		T63	1		T64	1
auto[0]	auto[1]	valid[0]	auto[1]	222	1			T16	2		T17	1		T20	6
auto[0]	auto[1]	valid[1]	auto[0]	41	1			T18	2		T70	1		T91	2
auto[0]	auto[1]	valid[1]	auto[1]	225	1			T16	2		T17	3		T20	6
auto[0]	auto[1]	valid[2]	auto[0]	42	1			T18	1		T61	1		T64	1
auto[0]	auto[1]	valid[2]	auto[1]	212	1			T16	3		T17	3		T20	4
auto[0]	auto[1]	valid[3]	auto[0]	40	1			T18	1		T63	1		T102	1
auto[0]	auto[1]	valid[3]	auto[1]	229	1			T16	6		T20	6		T21	2
auto[0]	auto[1]	valid[4]	auto[0]	35	1			T63	1		T102	2		T70	1
auto[0]	auto[1]	valid[4]	auto[1]	260	1			T16	2		T17	1		T20	8
auto[1]	auto[0]	valid[0]	auto[0]	32	1			T18	1		T19	1		T61	1
auto[1]	auto[0]	valid[1]	auto[0]	34	1			T63	1		T102	1		T403	1
auto[1]	auto[0]	valid[2]	auto[0]	38	1			T18	4		T61	1		T64	1
auto[1]	auto[0]	valid[3]	auto[0]	26	1			T64	1		T91	1		T373	1
auto[1]	auto[0]	valid[4]	auto[0]	33	1			T63	1		T91	1		T71	4
auto[1]	auto[1]	valid[0]	auto[0]	27	1			T64	2		T70	1		T91	2
auto[1]	auto[1]	valid[1]	auto[0]	23	1			T18	1		T61	1		T64	1
auto[1]	auto[1]	valid[2]	auto[0]	31	1			T18	1		T61	1		T63	1
auto[1]	auto[1]	valid[3]	auto[0]	26	1			T18	2		T61	1		T70	1
auto[1]	auto[1]	valid[4]	auto[0]	38	1			T18	2		T63	1		T64	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal