Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19772

1

T8

20

T15

9

T18

623

auto[1]

21314

1

T16

346

T17

385

T20

638

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33843

1

T8

7

T15

4

T16

346

auto[1]

7243

1

T8

13

T15

5

T18

204

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	21346	1			T8	7		T15	3		T16	170
others[1]	3506	1			T8	2		T15	1		T16	29
others[2]	3485	1			T8	2		T15	2		T16	24
others[3]	3873	1			T8	3		T15	1		T16	37
interest[1]	2279	1			T8	1		T15	1		T16	20
interest[4]	14182	1			T8	1		T15	3		T16	106
interest[64]	6597	1			T8	5		T15	1		T16	66

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	6429	1			T8	3		T15	2		T18	214
auto[0]	auto[0]	others[1]	1062	1			T8	1		T18	38		T19	2
auto[0]	auto[0]	others[2]	1022	1			T15	1		T18	38		T59	1
auto[0]	auto[0]	others[3]	1184	1			T8	1		T18	43		T61	13
auto[0]	auto[0]	interest[1]	732	1			T8	1		T18	18		T19	2
auto[0]	auto[0]	interest[4]	4190	1			T8	1		T15	2		T18	138
auto[0]	auto[0]	interest[64]	2100	1			T8	1		T15	1		T18	68
auto[0]	auto[1]	others[0]	11226	1			T16	170		T17	185		T20	319
auto[0]	auto[1]	others[1]	1810	1			T16	29		T17	32		T20	56
auto[0]	auto[1]	others[2]	1813	1			T16	24		T17	35		T20	49
auto[0]	auto[1]	others[3]	1984	1			T16	37		T17	43		T20	67
auto[0]	auto[1]	interest[1]	1148	1			T16	20		T17	21		T20	32
auto[0]	auto[1]	interest[4]	7550	1			T16	106		T17	117		T20	206
auto[0]	auto[1]	interest[64]	3333	1			T16	66		T17	69		T20	115
auto[1]	auto[0]	others[0]	3691	1			T8	4		T15	1		T18	95
auto[1]	auto[0]	others[1]	634	1			T8	1		T15	1		T18	19
auto[1]	auto[0]	others[2]	650	1			T8	2		T15	1		T18	20
auto[1]	auto[0]	others[3]	705	1			T8	2		T15	1		T18	25
auto[1]	auto[0]	interest[1]	399	1			T15	1		T18	9		T61	3
auto[1]	auto[0]	interest[4]	2442	1			T15	1		T18	62		T19	1
auto[1]	auto[0]	interest[64]	1164	1			T8	4		T18	36		T19	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal