Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	524	1			T1	11		T22	14		T38	17
all_values[1]	524	1			T1	11		T22	14		T38	17
all_values[2]	524	1			T1	11		T22	14		T38	17
all_values[3]	524	1			T1	11		T22	14		T38	17
all_values[4]	524	1			T1	11		T22	14		T38	17
all_values[5]	524	1			T1	11		T22	14		T38	17
all_values[6]	524	1			T1	11		T22	14		T38	17
all_values[7]	524	1			T1	11		T22	14		T38	17

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2211

1

T1

46

T22

59

T38

66

auto[1]

1981

1

T1

42

T22

53

T38

70

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1741

1

T1

37

T22

46

T38

64

auto[1]

2451

1

T1

51

T22

66

T38

72

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2441

1

T1

58

T22

60

T38

82

auto[1]

1751

1

T1

30

T22

52

T38

54

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	104	1			T1	5		T22	3		T38	5
all_values[0]	auto[0]	auto[0]	auto[1]	40	1			T22	2		T38	1		T347	2
all_values[0]	auto[0]	auto[1]	auto[0]	98	1			T1	2		T22	4		T38	3
all_values[0]	auto[0]	auto[1]	auto[1]	66	1			T1	2		T22	1		T39	1
all_values[0]	auto[1]	auto[0]	auto[1]	107	1			T22	1		T38	3		T39	1
all_values[0]	auto[1]	auto[1]	auto[1]	109	1			T1	2		T22	3		T38	5
all_values[1]	auto[0]	auto[0]	auto[0]	110	1			T1	3		T22	3		T38	3
all_values[1]	auto[0]	auto[0]	auto[1]	57	1			T38	1		T39	2		T348	1
all_values[1]	auto[0]	auto[1]	auto[0]	99	1			T1	4		T22	4		T38	2
all_values[1]	auto[0]	auto[1]	auto[1]	44	1			T22	1		T38	2		T39	1
all_values[1]	auto[1]	auto[0]	auto[1]	120	1			T1	3		T22	5		T38	4
all_values[1]	auto[1]	auto[1]	auto[1]	94	1			T1	1		T22	1		T38	5
all_values[2]	auto[0]	auto[0]	auto[0]	92	1			T1	2		T22	5		T38	4
all_values[2]	auto[0]	auto[0]	auto[1]	54	1			T1	1		T38	2		T39	1
all_values[2]	auto[0]	auto[1]	auto[0]	107	1			T1	5		T22	4		T38	1
all_values[2]	auto[0]	auto[1]	auto[1]	54	1			T1	1		T38	3		T39	2
all_values[2]	auto[1]	auto[0]	auto[1]	118	1			T1	2		T22	1		T38	3
all_values[2]	auto[1]	auto[1]	auto[1]	99	1			T22	4		T38	4		T39	2
all_values[3]	auto[0]	auto[0]	auto[0]	105	1			T1	2		T22	4		T39	1
all_values[3]	auto[0]	auto[0]	auto[1]	51	1			T1	1		T22	1		T38	2
all_values[3]	auto[0]	auto[1]	auto[0]	99	1			T22	2		T38	8		T39	4
all_values[3]	auto[0]	auto[1]	auto[1]	54	1			T1	3		T22	2		T348	1
all_values[3]	auto[1]	auto[0]	auto[1]	121	1			T1	4		T22	2		T38	3
all_values[3]	auto[1]	auto[1]	auto[1]	94	1			T1	1		T22	3		T38	4
all_values[4]	auto[0]	auto[0]	auto[0]	119	1			T22	3		T38	4		T348	7
all_values[4]	auto[0]	auto[0]	auto[1]	49	1			T1	3		T38	2		T39	2
all_values[4]	auto[0]	auto[1]	auto[0]	71	1			T22	3		T38	1		T39	1
all_values[4]	auto[0]	auto[1]	auto[1]	55	1			T1	5		T22	1		T38	2
all_values[4]	auto[1]	auto[0]	auto[1]	126	1			T1	1		T22	4		T38	4
all_values[4]	auto[1]	auto[1]	auto[1]	104	1			T1	2		T22	3		T38	4
all_values[5]	auto[0]	auto[0]	auto[0]	157	1			T1	3		T22	4		T38	3
all_values[5]	auto[0]	auto[1]	auto[0]	138	1			T1	4		T22	1		T38	7
all_values[5]	auto[1]	auto[0]	auto[1]	127	1			T1	1		T22	2		T38	5
all_values[5]	auto[1]	auto[1]	auto[1]	102	1			T1	3		T22	7		T38	2
all_values[6]	auto[0]	auto[0]	auto[0]	126	1			T1	3		T22	1		T38	4
all_values[6]	auto[0]	auto[0]	auto[1]	39	1			T1	2		T22	3		T39	1
all_values[6]	auto[0]	auto[1]	auto[0]	121	1			T1	1		T38	11		T39	3
all_values[6]	auto[0]	auto[1]	auto[1]	33	1			T1	1		T348	2		T347	1
all_values[6]	auto[1]	auto[0]	auto[1]	108	1			T1	2		T22	7		T38	2
all_values[6]	auto[1]	auto[1]	auto[1]	97	1			T1	2		T22	3		T39	1
all_values[7]	auto[0]	auto[0]	auto[0]	104	1			T1	2		T22	3		T38	5
all_values[7]	auto[0]	auto[0]	auto[1]	57	1			T1	2		T22	2		T38	2
all_values[7]	auto[0]	auto[1]	auto[0]	91	1			T1	1		T22	2		T38	3
all_values[7]	auto[0]	auto[1]	auto[1]	47	1			T22	1		T38	1		T39	2
all_values[7]	auto[1]	auto[0]	auto[1]	120	1			T1	4		T22	3		T38	4
all_values[7]	auto[1]	auto[1]	auto[1]	105	1			T1	2		T22	3		T38	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal