Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	274575	1			T1	1		T3	222		T4	1
all_values[1]	274575	1			T1	1		T3	222		T4	1
all_values[2]	274575	1			T1	1		T3	222		T4	1
all_values[3]	274575	1			T1	1		T3	222		T4	1
all_values[4]	274575	1			T1	1		T3	222		T4	1
all_values[5]	274575	1			T1	1		T3	222		T4	1
all_values[6]	274575	1			T1	1		T3	222		T4	1
all_values[7]	274575	1			T1	1		T3	222		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2194452

1

T1

8

T3

1776

T4

8

auto[1]

2148

1

T32

49

T33

79

T34

58

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2194664

1

T1

8

T3

1772

T4

8

auto[1]

1936

1

T3

4

T12

2

T15

4

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	274221	1			T1	1		T3	222		T4	1
all_values[0]	auto[0]	auto[1]	115	1			T32	3		T34	2		T40	2
all_values[0]	auto[1]	auto[0]	136	1			T32	1		T33	6		T34	7
all_values[0]	auto[1]	auto[1]	103	1			T32	4		T33	5		T34	3
all_values[1]	auto[0]	auto[0]	274188	1			T1	1		T3	222		T4	1
all_values[1]	auto[0]	auto[1]	116	1			T32	2		T33	2		T34	5
all_values[1]	auto[1]	auto[0]	140	1			T32	3		T33	14		T34	3
all_values[1]	auto[1]	auto[1]	131	1			T32	1		T33	1		T34	1
all_values[2]	auto[0]	auto[0]	274193	1			T1	1		T3	222		T4	1
all_values[2]	auto[0]	auto[1]	101	1			T33	4		T34	5		T40	3
all_values[2]	auto[1]	auto[0]	163	1			T32	2		T33	3		T34	5
all_values[2]	auto[1]	auto[1]	118	1			T32	4		T33	2		T34	1
all_values[3]	auto[0]	auto[0]	274212	1			T1	1		T3	222		T4	1
all_values[3]	auto[0]	auto[1]	120	1			T296	2		T32	1		T33	1
all_values[3]	auto[1]	auto[0]	148	1			T32	6		T33	5		T34	2
all_values[3]	auto[1]	auto[1]	95	1			T32	3		T33	4		T34	1
all_values[4]	auto[0]	auto[0]	274163	1			T1	1		T3	222		T4	1
all_values[4]	auto[0]	auto[1]	139	1			T7	3		T80	4		T297	22
all_values[4]	auto[1]	auto[0]	170	1			T32	5		T33	6		T34	7
all_values[4]	auto[1]	auto[1]	103	1			T32	5		T33	2		T34	3
all_values[5]	auto[0]	auto[0]	274021	1			T1	1		T3	218		T4	1
all_values[5]	auto[0]	auto[1]	295	1			T3	4		T12	2		T15	4
all_values[5]	auto[1]	auto[0]	169	1			T32	5		T33	7		T34	8
all_values[5]	auto[1]	auto[1]	90	1			T32	3		T33	5		T34	1
all_values[6]	auto[0]	auto[0]	274182	1			T1	1		T3	222		T4	1
all_values[6]	auto[0]	auto[1]	106	1			T32	4		T33	5		T34	4
all_values[6]	auto[1]	auto[0]	178	1			T33	7		T34	5		T40	11
all_values[6]	auto[1]	auto[1]	109	1			T32	4		T33	3		T40	1
all_values[7]	auto[0]	auto[0]	274192	1			T1	1		T3	222		T4	1
all_values[7]	auto[0]	auto[1]	88	1			T32	6		T33	4		T34	3
all_values[7]	auto[1]	auto[0]	188	1			T32	1		T33	5		T34	7
all_values[7]	auto[1]	auto[1]	107	1			T32	2		T33	4		T34	4