Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
72.13	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	33	51	60.71

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	29	19	39.58	100	1	1	0
cr_modeXdummyXnum_lanes	36	4	32	88.89	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	1074	1			T1	6		T4	2		T5	6
auto[SpiFlashAddrCfg]	867	1			T5	8		T6	2		T8	2
auto[SpiFlashAddr3b]	1013	1			T4	14		T5	4		T6	4
auto[SpiFlashAddr4b]	866	1			T4	4		T5	2		T6	10

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2962

1

T1

6

T5

20

T6

22

auto[1]

858

1

T4

20

T64

6

T65

20

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1999

1

T1

6

T4

6

T5

10

auto[1]

1821

1

T4

14

T5

10

T6

12

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1606	1			T1	6		T4	16		T5	14
values[1]	80	1			T63	2		T72	8		T223	2
values[2]	163	1			T4	4		T83	3		T63	2
values[3]	198	1			T5	2		T8	2		T79	4
values[4]	164	1			T83	6		T68	2		T95	4
values[5]	183	1			T81	3		T65	4		T70	2
values[6]	165	1			T6	4		T83	5		T174	2
values[7]	159	1			T80	3		T64	2		T113	2
values[8]	1102	1			T5	4		T6	6		T7	18

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3346

1

T1

6

T4

20

T5

20

auto[1]

474

1

T7

18

T83

20

T80

7

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3666

1

T1

6

T4

12

T5

20

write

154

1

T4

8

T6

2

T63

6

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1717

1

T1

6

T4

4

T5

8

valids[0x1]

2103

1

T4

16

T5

12

T6

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	232	1			T5	4		T79	6		T42	8
internal_process_ops[0x5a]	184	1			T5	2		T6	2		T63	6
internal_process_ops[0x05]	196	1			T6	2		T79	2		T63	2
internal_process_ops[0x35]	142	1			T4	2		T5	2		T6	2
internal_process_ops[0x15]	144	1			T6	2		T9	2		T95	4
internal_process_ops[0x03]	276	1			T79	2		T83	5		T68	6
internal_process_ops[0x0b]	286	1			T7	2		T79	4		T83	6
internal_process_ops[0x3b]	249	1			T7	5		T83	4		T81	6
internal_process_ops[0x6b]	232	1			T7	6		T63	2		T95	4
internal_process_ops[0xbb]	254	1			T5	2		T7	5		T8	2
internal_process_ops[0xeb]	215	1			T6	4		T79	2		T83	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3768

1

T1

6

T4

12

T5

20

auto[1]

52

1

T4

8

T64

2

T65

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3820

1

T1

6

T4

20

T5

20

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	29	19	39.58	29
Automatically Generated Cross Bins	48	29	19	39.58	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[read]	[auto[SpiFlashAddrDisabled]]	*	[auto[0]]	--	--	2
[auto[1]]	[write]	*	*	*	--	--	16

Uncovered bins

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[read]	[auto[SpiFlashAddrCfg] , auto[SpiFlashAddr3b] , auto[SpiFlashAddr4b]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

848

1

T1

6

T5

6

T6

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

206

1

T4

2

T65

2

T70

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

484

1

T5

8

T6

2

T8

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

174

1

T64

2

T65

8

T70

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

610

1

T5

4

T6

2

T63

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

224

1

T4

10

T64

2

T176

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

444

1

T5

2

T6

10

T79

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

202

1

T65

6

T70

8

T209

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8

1

T63

2

T85

2

T231

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

12

1

T65

4

T74

2

T67

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

30

1

T63

2

T173

8

T223

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

6

1

T72

2

T73

2

T295

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

44

1

T6

2

T63

2

T68

6

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

8

1

T4

4

T70

4

-

-

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

20

1

T68

4

T229

2

T188

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

26

1

T4

4

T64

2

T71

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

173

1

T81

12

T82

2

T296

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

127

1

T7

5

T83

6

T82

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

174

1

T7

13

T83

14

T80

7

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	4	32	88.89	4

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[1]]	*	--	--	2

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[0]]	[valids[0x0]]	0	1	1

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	338	1			T1	6		T5	4		T6	2
auto[0]	values[0]	valids[0x1]	1188	1			T4	16		T5	10		T6	10
auto[0]	values[1]	valids[0x1]	80	1			T63	2		T72	8		T223	2
auto[0]	values[2]	valids[0x0]	74	1			T4	4		T63	2		T92	2
auto[0]	values[2]	valids[0x1]	52	1			T218	2		T172	4		T233	4
auto[0]	values[3]	valids[0x0]	92	1			T5	2		T8	2		T95	2
auto[0]	values[3]	valids[0x1]	70	1			T79	4		T68	2		T91	2
auto[0]	values[4]	valids[0x0]	86	1			T68	2		T253	2		T229	6
auto[0]	values[4]	valids[0x1]	36	1			T95	4		T29	8		T162	2
auto[0]	values[5]	valids[0x0]	56	1			T70	2		T177	4		T29	6
auto[0]	values[5]	valids[0x1]	80	1			T65	4		T27	4		T71	6
auto[0]	values[6]	valids[0x0]	80	1			T6	4		T259	4		T29	2
auto[0]	values[6]	valids[0x1]	72	1			T174	2		T162	4		T171	2
auto[0]	values[7]	valids[0x0]	80	1			T64	2		T113	2		T259	6
auto[0]	values[7]	valids[0x1]	58	1			T173	2		T177	2		T72	4
auto[0]	values[8]	valids[0x0]	604	1			T5	2		T6	4		T79	2
auto[0]	values[8]	valids[0x1]	300	1			T5	2		T6	2		T79	2
auto[1]	values[0]	valids[0x1]	80	1			T82	3		T297	5		T298	1
auto[1]	values[2]	valids[0x0]	27	1			T83	3		T80	4		T161	3
auto[1]	values[2]	valids[0x1]	10	1			T299	4		T300	5		T301	1
auto[1]	values[3]	valids[0x0]	32	1			T82	4		T302	2		T303	5
auto[1]	values[3]	valids[0x1]	4	1			T304	4		-	-		-	-
auto[1]	values[4]	valids[0x0]	37	1			T83	6		T81	6		T296	9
auto[1]	values[4]	valids[0x1]	5	1			T161	5		-	-		-	-
auto[1]	values[5]	valids[0x0]	32	1			T81	3		T305	6		T306	4
auto[1]	values[5]	valids[0x1]	15	1			T307	8		T308	5		T309	2
auto[1]	values[6]	valids[0x0]	5	1			T305	2		T310	3		-	-
auto[1]	values[6]	valids[0x1]	8	1			T83	5		T311	3		-	-
auto[1]	values[7]	valids[0x0]	16	1			T80	3		T310	7		T308	1
auto[1]	values[7]	valids[0x1]	5	1			T301	5		-	-		-	-
auto[1]	values[8]	valids[0x0]	158	1			T7	16		T83	6		T81	3
auto[1]	values[8]	valids[0x1]	40	1			T7	2		T298	6		T305	2