Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
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Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1486554 1 T1 4978 T4 1 T5 1025


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1397112 1 T1 4978 T4 1 T5 1
auto[1] 89442 1 T5 1024 T8 256 T9 5636


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 317894 1 T1 495 T4 1 T5 1025
auto[524288:1048575] 160501 1 T1 133 T7 240 T8 2
auto[1048576:1572863] 166333 1 T1 1454 T7 1049 T8 135
auto[1572864:2097151] 221421 1 T1 183 T7 2224 T8 17
auto[2097152:2621439] 160762 1 T1 383 T7 4997 T10 2486
auto[2621440:3145727] 136382 1 T1 1258 T7 37 T10 1135
auto[3145728:3670015] 164761 1 T1 886 T7 7538 T10 4
auto[3670016:4194303] 158500 1 T1 186 T7 1869 T8 309


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 102415 1 T1 118 T4 1 T5 1025
auto[1] 1384139 1 T1 4860 T7 19485 T8 410


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1486554 1 T1 4978 T4 1 T5 1025


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 235143 1 T1 495 T4 1 T5 1
auto[0] auto[0] auto[0:524287] auto[1] 82751 1 T5 1024 T8 130 T9 5636
auto[0] auto[0] auto[524288:1048575] auto[0] 159424 1 T1 133 T7 240 T8 2
auto[0] auto[0] auto[524288:1048575] auto[1] 1077 1 T92 107 T164 1 T165 256
auto[0] auto[0] auto[1048576:1572863] auto[0] 165732 1 T1 1454 T7 1049 T8 9
auto[0] auto[0] auto[1048576:1572863] auto[1] 601 1 T8 126 T95 210 T92 2
auto[0] auto[0] auto[1572864:2097151] auto[0] 219763 1 T1 183 T7 2224 T8 17
auto[0] auto[0] auto[1572864:2097151] auto[1] 1658 1 T166 3 T165 256 T167 245
auto[0] auto[0] auto[2097152:2621439] auto[0] 159674 1 T1 383 T7 4997 T10 2486
auto[0] auto[0] auto[2097152:2621439] auto[1] 1088 1 T79 5 T167 11 T168 3
auto[0] auto[0] auto[2621440:3145727] auto[0] 135293 1 T1 1258 T7 37 T10 1135
auto[0] auto[0] auto[2621440:3145727] auto[1] 1089 1 T169 4 T168 12 T170 814
auto[0] auto[0] auto[3145728:3670015] auto[0] 163595 1 T1 886 T7 7538 T10 4
auto[0] auto[0] auto[3145728:3670015] auto[1] 1166 1 T92 24 T169 295 T167 256
auto[0] auto[0] auto[3670016:4194303] auto[0] 158488 1 T1 186 T7 1869 T8 309
auto[0] auto[0] auto[3670016:4194303] auto[1] 12 1 T95 11 T166 1 - -


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 102415 1 T1 118 T4 1 T5 1025
auto[0] auto[0] auto[1] 1384139 1 T1 4860 T7 19485 T8 410

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