Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
77.40	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	33	95	74.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	33	95	74.22	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2488

1

T1

6

T5

20

T6

22

auto[1]

858

1

T4

20

T64

6

T65

20

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	404	1			T10	2		T79	18		T42	12
values[1]	422	1			T5	20		T64	6		T259	14
values[2]	520	1			T63	18		T113	4		T114	8
values[3]	270	1			T174	2		T89	22		T65	20
values[4]	530	1			T43	16		T115	2		T69	30
values[5]	464	1			T4	20		T92	26		T25	22
values[6]	382	1			T1	6		T68	28		T28	8
values[7]	354	1			T6	22		T8	4		T9	4

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	392	1			T174	2		T91	18		T65	20
values[1]	298	1			T173	22		T253	2		T44	20
values[2]	382	1			T95	14		T89	22		T85	14
values[3]	410	1			T8	4		T63	18		T68	28
values[4]	420	1			T42	12		T27	24		T69	30
values[5]	398	1			T6	22		T79	18		T175	14
values[6]	662	1			T4	20		T9	4		T43	16
values[7]	384	1			T1	6		T5	20		T10	2

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	33	95	74.22	33

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[values[3]]	0	1	1
[auto[0]]	[values[5]]	[values[0]]	0	1	1
[auto[1]]	[values[0]]	[values[0]]	0	1	1
[auto[1]]	[values[0]]	[values[2] , values[3] , values[4]]	--	--	3
[auto[1]]	[values[1]]	[values[2] , values[3] , values[4] , values[5] , values[6]]	--	--	5
[auto[1]]	[values[2]]	[values[2]]	0	1	1
[auto[1]]	[values[3]]	[values[1]]	0	1	1
[auto[1]]	[values[3]]	[values[4] , values[5]]	--	--	2
[auto[1]]	[values[3]]	[values[7]]	0	1	1
[auto[1]]	[values[4]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[4]]	[values[4] , values[5]]	--	--	2
[auto[1]]	[values[5]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[5]]	[values[3]]	0	1	1
[auto[1]]	[values[5]]	[values[7]]	0	1	1
[auto[1]]	[values[6]]	[values[1]]	0	1	1
[auto[1]]	[values[6]]	[values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	5
[auto[1]]	[values[7]]	[values[1]]	0	1	1
[auto[1]]	[values[7]]	[values[5]]	0	1	1

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	26	1			T91	18		T246	8		-	-
auto[0]	values[0]	values[1]	16	1			T253	2		T250	2		T200	2
auto[0]	values[0]	values[2]	42	1			T95	14		T166	10		T312	18
auto[0]	values[0]	values[4]	80	1			T42	12		T313	16		T314	32
auto[0]	values[0]	values[5]	34	1			T79	18		T175	14		T315	2
auto[0]	values[0]	values[6]	58	1			T162	26		T241	8		T226	8
auto[0]	values[0]	values[7]	28	1			T10	2		T252	4		T167	18
auto[0]	values[1]	values[0]	68	1			T259	14		T242	4		T292	32
auto[0]	values[1]	values[1]	58	1			T173	22		T44	20		T186	4
auto[0]	values[1]	values[2]	24	1			T234	8		T210	16		-	-
auto[0]	values[1]	values[3]	22	1			T178	2		T255	12		T316	8
auto[0]	values[1]	values[4]	60	1			T261	12		T57	14		T193	14
auto[0]	values[1]	values[5]	10	1			T317	10		-	-		-	-
auto[0]	values[1]	values[6]	102	1			T29	32		T229	26		T286	12
auto[0]	values[1]	values[7]	20	1			T5	20		-	-		-	-
auto[0]	values[2]	values[0]	66	1			T177	14		T188	20		T318	10
auto[0]	values[2]	values[1]	28	1			T110	24		T319	4		-	-
auto[0]	values[2]	values[2]	8	1			T269	8		-	-		-	-
auto[0]	values[2]	values[3]	56	1			T63	18		T114	8		T260	30
auto[0]	values[2]	values[4]	12	1			T224	2		T94	10		-	-
auto[0]	values[2]	values[5]	70	1			T66	20		T204	8		T76	24
auto[0]	values[2]	values[6]	60	1			T113	4		T270	22		T289	8
auto[0]	values[2]	values[7]	38	1			T320	14		T321	18		T322	6
auto[0]	values[3]	values[0]	22	1			T174	2		T281	18		T195	2
auto[0]	values[3]	values[1]	16	1			T87	12		T262	4		-	-
auto[0]	values[3]	values[2]	36	1			T89	22		T85	14		-	-
auto[0]	values[3]	values[3]	6	1			T219	6		-	-		-	-
auto[0]	values[3]	values[4]	38	1			T27	24		T267	6		T323	8
auto[0]	values[3]	values[5]	14	1			T93	10		T276	4		-	-
auto[0]	values[3]	values[6]	44	1			T215	14		T26	4		T191	26
auto[0]	values[3]	values[7]	32	1			T231	24		T272	8		-	-
auto[0]	values[4]	values[0]	38	1			T115	2		T324	6		T325	10
auto[0]	values[4]	values[1]	38	1			T192	6		T268	26		T326	6
auto[0]	values[4]	values[2]	28	1			T194	8		T257	10		T327	10
auto[0]	values[4]	values[3]	66	1			T328	8		T77	16		T208	34
auto[0]	values[4]	values[4]	76	1			T69	30		T171	16		T258	22
auto[0]	values[4]	values[5]	70	1			T232	8		T329	22		T330	16
auto[0]	values[4]	values[6]	72	1			T43	16		T183	30		T189	4
auto[0]	values[4]	values[7]	40	1			T278	10		T169	2		T331	18
auto[0]	values[5]	values[1]	14	1			T203	8		T277	6		-	-
auto[0]	values[5]	values[2]	12	1			T90	12		-	-		-	-
auto[0]	values[5]	values[3]	30	1			T279	12		T332	18		-	-
auto[0]	values[5]	values[4]	24	1			T190	4		T78	20		-	-
auto[0]	values[5]	values[5]	40	1			T333	20		T212	20		-	-
auto[0]	values[5]	values[6]	80	1			T92	26		T25	22		T116	10
auto[0]	values[5]	values[7]	70	1			T205	12		T291	22		T282	18
auto[0]	values[6]	values[0]	44	1			T223	26		T265	18		-	-
auto[0]	values[6]	values[1]	20	1			T227	6		T197	14		-	-
auto[0]	values[6]	values[2]	74	1			T233	18		T283	14		T266	8
auto[0]	values[6]	values[3]	104	1			T68	28		T28	8		T271	24
auto[0]	values[6]	values[4]	4	1			T244	4		-	-		-	-
auto[0]	values[6]	values[5]	60	1			T230	20		T213	14		T293	26
auto[0]	values[6]	values[6]	12	1			T168	12		-	-		-	-
auto[0]	values[6]	values[7]	12	1			T1	6		T164	6		-	-
auto[0]	values[7]	values[0]	40	1			T211	10		T225	4		T334	4
auto[0]	values[7]	values[1]	12	1			T218	10		T335	2		-	-
auto[0]	values[7]	values[2]	40	1			T243	10		T248	18		T196	12
auto[0]	values[7]	values[3]	4	1			T8	4		-	-		-	-
auto[0]	values[7]	values[4]	52	1			T159	2		T336	28		T290	4
auto[0]	values[7]	values[5]	46	1			T6	22		T185	24		-	-
auto[0]	values[7]	values[6]	58	1			T9	4		T274	10		T288	12
auto[0]	values[7]	values[7]	14	1			T275	14		-	-		-	-
auto[1]	values[0]	values[1]	26	1			T337	26		-	-		-	-
auto[1]	values[0]	values[5]	30	1			T236	30		-	-		-	-
auto[1]	values[0]	values[6]	58	1			T75	6		T338	26		T220	26
auto[1]	values[0]	values[7]	6	1			T228	6		-	-		-	-
auto[1]	values[1]	values[0]	30	1			T339	30		-	-		-	-
auto[1]	values[1]	values[1]	22	1			T182	22		-	-		-	-
auto[1]	values[1]	values[7]	6	1			T64	6		-	-		-	-
auto[1]	values[2]	values[0]	8	1			T340	8		-	-		-	-
auto[1]	values[2]	values[1]	48	1			T245	24		T341	4		T295	20
auto[1]	values[2]	values[3]	40	1			T73	24		T237	16		-	-
auto[1]	values[2]	values[4]	16	1			T287	16		-	-		-	-
auto[1]	values[2]	values[5]	4	1			T280	4		-	-		-	-
auto[1]	values[2]	values[6]	18	1			T214	18		-	-		-	-
auto[1]	values[2]	values[7]	48	1			T294	30		T342	18		-	-
auto[1]	values[3]	values[0]	20	1			T65	20		-	-		-	-
auto[1]	values[3]	values[2]	10	1			T67	10		-	-		-	-
auto[1]	values[3]	values[3]	12	1			T249	12		-	-		-	-
auto[1]	values[3]	values[6]	20	1			T343	20		-	-		-	-
auto[1]	values[4]	values[3]	56	1			T285	24		T344	16		T345	16
auto[1]	values[4]	values[6]	14	1			T235	14		-	-		-	-
auto[1]	values[4]	values[7]	32	1			T172	22		T222	6		T201	4
auto[1]	values[5]	values[2]	74	1			T247	26		T346	30		T187	18
auto[1]	values[5]	values[4]	38	1			T71	14		T238	24		-	-
auto[1]	values[5]	values[5]	20	1			T347	20		-	-		-	-
auto[1]	values[5]	values[6]	62	1			T4	20		T70	18		T72	24
auto[1]	values[6]	values[0]	22	1			T273	22		-	-		-	-
auto[1]	values[6]	values[2]	30	1			T74	12		T217	18		-	-
auto[1]	values[7]	values[0]	8	1			T206	8		-	-		-	-
auto[1]	values[7]	values[2]	4	1			T209	4		-	-		-	-
auto[1]	values[7]	values[3]	14	1			T251	14		-	-		-	-
auto[1]	values[7]	values[4]	20	1			T176	2		T264	18		-	-
auto[1]	values[7]	values[6]	4	1			T348	4		-	-		-	-
auto[1]	values[7]	values[7]	38	1			T202	38		-	-		-	-