Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.52	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	4	56	93.33

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	4	56	93.33	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	84	1			T92	18		T114	2		T215	2
auto[ReadAddrCrossIntoMailbox]	20	1			T215	6		T261	2		T184	4
auto[ReadAddrCrossOutOfMailbox]	26	1			T215	2		T272	4		T184	2
auto[ReadAddrCrossAllMailbox]	52	1			T114	6		T253	2		T159	2
auto[ReadAddrOutsideMailbox]	834	1			T5	2		T6	4		T8	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

508

1

T5

1

T6

2

T8

1

auto[1]

508

1

T5

1

T6

2

T8

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	194	1			T79	2		T68	6		T95	4
read_ops[0x0b]	184	1			T79	4		T63	2		T68	2
read_ops[0x3b]	180	1			T114	4		T85	2		T259	6
read_ops[0x6b]	150	1			T63	2		T95	4		T92	2
read_ops[0xbb]	156	1			T5	2		T8	2		T68	2
read_ops[0xeb]	152	1			T6	4		T79	2		T92	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	4	56	93.33	4

Automatically Generated Cross Bins for cr_all

Element holes

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	NUMBER	STATUS
[read_ops[0x0b]]	[auto[ReadAddrCrossOutOfMailbox]]	*	--	--	2
[read_ops[0x6b]]	[auto[ReadAddrCrossIntoMailbox]]	*	--	--	2

Covered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	5	1			T92	1		T171	1		T212	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	5	1			T92	1		T171	1		T212	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	5	1			T215	2		T261	1		T284	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	5	1			T215	2		T261	1		T284	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T284	2		T212	1		T226	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T284	2		T212	1		T226	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	8	1			T286	1		T204	2		T261	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	8	1			T286	1		T204	2		T261	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	74	1			T79	1		T68	3		T95	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	74	1			T79	1		T68	3		T95	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	12	1			T92	5		T164	1		T248	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	12	1			T92	5		T164	1		T248	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T184	2		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T184	2		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T215	1		T184	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T215	1		T184	1		-	-
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	76	1			T79	2		T63	1		T68	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	76	1			T79	2		T63	1		T68	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	9	1			T114	1		T164	1		T248	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	9	1			T114	1		T164	1		T248	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T317	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T317	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T272	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T272	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	7	1			T114	1		T204	1		T212	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	7	1			T114	1		T204	1		T212	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	72	1			T85	1		T259	3		T177	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	72	1			T85	1		T259	3		T177	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	4	1			T92	1		T215	1		T171	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	4	1			T92	1		T215	1		T171	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T212	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T212	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T114	1		T267	1		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T114	1		T267	1		-	-
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	68	1			T63	1		T95	2		T113	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	68	1			T63	1		T95	2		T113	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	6	1			T92	1		T171	1		T286	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	6	1			T92	1		T171	1		T286	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T212	1		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T212	1		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	5	1			T272	1		T184	1		T212	3
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	5	1			T272	1		T184	1		T212	3
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T253	1		T159	1		T215	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T253	1		T159	1		T215	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	63	1			T5	1		T8	1		T68	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	63	1			T5	1		T8	1		T68	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	6	1			T92	1		T171	2		T234	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	6	1			T92	1		T171	2		T234	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T215	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T215	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T215	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T215	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T114	1		T286	2		T57	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T114	1		T286	2		T57	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	64	1			T6	2		T79	1		T91	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	64	1			T6	2		T79	1		T91	1