Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	274575	1			T1	1		T3	222		T4	1
all_pins[1]	274575	1			T1	1		T3	222		T4	1
all_pins[2]	274575	1			T1	1		T3	222		T4	1
all_pins[3]	274575	1			T1	1		T3	222		T4	1
all_pins[4]	274575	1			T1	1		T3	222		T4	1
all_pins[5]	274575	1			T1	1		T3	222		T4	1
all_pins[6]	274575	1			T1	1		T3	222		T4	1
all_pins[7]	274575	1			T1	1		T3	222		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2195744	1			T1	8		T3	1776		T4	8
values[0x1]	856	1			T32	26		T33	26		T34	14
transitions[0x0=>0x1]	624	1			T32	13		T33	20		T34	14
transitions[0x1=>0x0]	636	1			T32	14		T33	20		T34	14

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	274472	1			T1	1		T3	222		T4	1
all_pins[0]	values[0x1]	103	1			T32	4		T33	5		T34	3
all_pins[0]	transitions[0x0=>0x1]	66	1			T32	3		T33	4		T34	3
all_pins[0]	transitions[0x1=>0x0]	94	1			T34	1		T40	5		T366	1
all_pins[1]	values[0x0]	274444	1			T1	1		T3	222		T4	1
all_pins[1]	values[0x1]	131	1			T32	1		T33	1		T34	1
all_pins[1]	transitions[0x0=>0x1]	96	1			T33	1		T34	1		T40	5
all_pins[1]	transitions[0x1=>0x0]	83	1			T32	3		T33	2		T34	1
all_pins[2]	values[0x0]	274457	1			T1	1		T3	222		T4	1
all_pins[2]	values[0x1]	118	1			T32	4		T33	2		T34	1
all_pins[2]	transitions[0x0=>0x1]	90	1			T32	2		T33	1		T34	1
all_pins[2]	transitions[0x1=>0x0]	67	1			T32	1		T33	3		T34	1
all_pins[3]	values[0x0]	274480	1			T1	1		T3	222		T4	1
all_pins[3]	values[0x1]	95	1			T32	3		T33	4		T34	1
all_pins[3]	transitions[0x0=>0x1]	69	1			T32	1		T33	4		T34	1
all_pins[3]	transitions[0x1=>0x0]	77	1			T32	3		T33	2		T34	3
all_pins[4]	values[0x0]	274472	1			T1	1		T3	222		T4	1
all_pins[4]	values[0x1]	103	1			T32	5		T33	2		T34	3
all_pins[4]	transitions[0x0=>0x1]	81	1			T32	2		T33	1		T34	3
all_pins[4]	transitions[0x1=>0x0]	68	1			T33	4		T34	1		T40	2
all_pins[5]	values[0x0]	274485	1			T1	1		T3	222		T4	1
all_pins[5]	values[0x1]	90	1			T32	3		T33	5		T34	1
all_pins[5]	transitions[0x0=>0x1]	69	1			T32	2		T33	3		T34	1
all_pins[5]	transitions[0x1=>0x0]	88	1			T32	3		T33	1		T40	1
all_pins[6]	values[0x0]	274466	1			T1	1		T3	222		T4	1
all_pins[6]	values[0x1]	109	1			T32	4		T33	3		T40	1
all_pins[6]	transitions[0x0=>0x1]	81	1			T32	2		T33	3		T40	1
all_pins[6]	transitions[0x1=>0x0]	79	1			T33	4		T34	4		T40	3
all_pins[7]	values[0x0]	274468	1			T1	1		T3	222		T4	1
all_pins[7]	values[0x1]	107	1			T32	2		T33	4		T34	4
all_pins[7]	transitions[0x0=>0x1]	72	1			T32	1		T33	3		T34	4
all_pins[7]	transitions[0x1=>0x0]	80	1			T32	4		T33	4		T34	3