Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
65.07	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	51	77	60.16

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	51	77	60.16	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	358	1			T5	20		T171	16		T172	22
values[1]	276	1			T8	4		T9	4		T27	24
values[2]	430	1			T1	6		T10	2		T92	26
values[3]	462	1			T68	28		T95	14		T43	16
values[4]	478	1			T91	18		T85	14		T173	22
values[5]	424	1			T42	12		T64	6		T89	22
values[6]	450	1			T4	20		T174	2		T70	18
values[7]	468	1			T6	22		T79	18		T63	18

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	358	1			T85	14		T175	14		T176	2
values[1]	384	1			T5	20		T95	14		T91	18
values[2]	440	1			T6	22		T8	4		T113	4
values[3]	468	1			T64	6		T25	22		T115	2
values[4]	466	1			T63	18		T42	12		T174	2
values[5]	434	1			T10	2		T43	16		T177	14
values[6]	368	1			T4	20		T68	28		T65	20
values[7]	428	1			T1	6		T9	4		T79	18

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3294

1

T1

6

T4

12

T5

20

auto[1]

52

1

T4

8

T64

2

T65

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	51	77	60.16	51

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	8
[auto[1]]	[values[2]]	*	--	--	8

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[1]]	[values[0] , values[1] , values[2] , values[3] , values[4]]	--	--	5
[auto[1]]	[values[1]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[3]]	[values[0] , values[1] , values[2] , values[3]]	--	--	4
[auto[1]]	[values[3]]	[values[5]]	0	1	1
[auto[1]]	[values[3]]	[values[7]]	0	1	1
[auto[1]]	[values[4]]	[values[0]]	0	1	1
[auto[1]]	[values[4]]	[values[2] , values[3] , values[4] , values[5] , values[6]]	--	--	5
[auto[1]]	[values[5]]	[values[1]]	0	1	1
[auto[1]]	[values[5]]	[values[4] , values[5] , values[6] , values[7]]	--	--	4
[auto[1]]	[values[6]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[6]]	[values[7]]	0	1	1
[auto[1]]	[values[7]]	[values[0] , values[1] , values[2] , values[3] , values[4]]	--	--	5
[auto[1]]	[values[7]]	[values[6] , values[7]]	--	--	2

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	12	1			T178	2		T179	4		T180	4
auto[0]	values[0]	values[1]	96	1			T5	20		T181	10		T182	22
auto[0]	values[0]	values[2]	76	1			T183	30		T184	22		T185	24
auto[0]	values[0]	values[3]	22	1			T186	4		T187	18		-	-
auto[0]	values[0]	values[4]	28	1			T188	20		T189	4		T190	4
auto[0]	values[0]	values[5]	54	1			T172	22		T191	26		T192	6
auto[0]	values[0]	values[6]	14	1			T193	14		-	-		-	-
auto[0]	values[0]	values[7]	56	1			T171	16		T194	8		T195	2
auto[0]	values[1]	values[0]	44	1			T176	2		T196	12		T197	14
auto[0]	values[1]	values[1]	46	1			T27	24		T198	22		-	-
auto[0]	values[1]	values[2]	32	1			T8	4		T199	28		-	-
auto[0]	values[1]	values[3]	52	1			T200	2		T94	10		T201	4
auto[0]	values[1]	values[4]	12	1			T28	8		T88	4		-	-
auto[0]	values[1]	values[5]	66	1			T202	34		T78	20		T168	12
auto[0]	values[1]	values[6]	8	1			T203	8		-	-		-	-
auto[0]	values[1]	values[7]	12	1			T9	4		T204	8		-	-
auto[0]	values[2]	values[0]	46	1			T205	12		T206	8		T207	10
auto[0]	values[2]	values[1]	34	1			T208	34		-	-		-	-
auto[0]	values[2]	values[2]	20	1			T209	4		T210	16		-	-
auto[0]	values[2]	values[3]	76	1			T25	22		T115	2		T93	10
auto[0]	values[2]	values[4]	44	1			T211	10		T212	20		T213	14
auto[0]	values[2]	values[5]	82	1			T10	2		T177	14		T214	18
auto[0]	values[2]	values[6]	44	1			T215	14		T216	12		T217	18
auto[0]	values[2]	values[7]	84	1			T1	6		T92	26		T218	10
auto[0]	values[3]	values[0]	54	1			T219	6		T220	26		T221	6
auto[0]	values[3]	values[1]	58	1			T95	14		T116	10		T222	6
auto[0]	values[3]	values[2]	50	1			T113	4		T57	14		T169	2
auto[0]	values[3]	values[3]	82	1			T223	26		T224	2		T225	4
auto[0]	values[3]	values[4]	18	1			T164	6		T75	4		T226	8
auto[0]	values[3]	values[5]	28	1			T43	16		T227	6		T228	6
auto[0]	values[3]	values[6]	80	1			T68	28		T65	16		T66	20
auto[0]	values[3]	values[7]	86	1			T229	26		T230	20		T110	24
auto[0]	values[4]	values[0]	54	1			T85	14		T231	24		T232	8
auto[0]	values[4]	values[1]	40	1			T91	18		T72	22		-	-
auto[0]	values[4]	values[2]	48	1			T69	30		T233	18		-	-
auto[0]	values[4]	values[3]	60	1			T26	4		T234	8		T235	14
auto[0]	values[4]	values[4]	116	1			T29	32		T236	30		T237	16
auto[0]	values[4]	values[5]	66	1			T238	24		T239	10		T240	10
auto[0]	values[4]	values[6]	54	1			T173	22		T241	8		T242	4
auto[0]	values[4]	values[7]	32	1			T243	10		T244	4		T245	18
auto[0]	values[5]	values[0]	46	1			T71	12		T246	8		T247	26
auto[0]	values[5]	values[1]	18	1			T248	18		-	-		-	-
auto[0]	values[5]	values[2]	104	1			T114	8		T162	26		T249	12
auto[0]	values[5]	values[3]	20	1			T64	4		T250	2		T251	14
auto[0]	values[5]	values[4]	52	1			T42	12		T90	12		T252	4
auto[0]	values[5]	values[5]	24	1			T253	2		T254	6		T255	12
auto[0]	values[5]	values[6]	80	1			T256	16		T257	10		T258	22
auto[0]	values[5]	values[7]	66	1			T89	22		T259	14		T260	30
auto[0]	values[6]	values[0]	24	1			T261	12		T262	4		T263	8
auto[0]	values[6]	values[1]	68	1			T264	18		T265	18		T266	8
auto[0]	values[6]	values[2]	40	1			T267	6		T268	26		T269	8
auto[0]	values[6]	values[3]	84	1			T159	2		T74	10		T270	22
auto[0]	values[6]	values[4]	86	1			T174	2		T70	14		T271	24
auto[0]	values[6]	values[5]	70	1			T73	22		T272	8		T273	22
auto[0]	values[6]	values[6]	50	1			T4	12		T274	10		T275	14
auto[0]	values[6]	values[7]	10	1			T276	4		T277	6		-	-
auto[0]	values[7]	values[0]	76	1			T175	14		T278	10		T279	12
auto[0]	values[7]	values[1]	22	1			T280	4		T281	18		-	-
auto[0]	values[7]	values[2]	60	1			T6	22		T44	20		T282	18
auto[0]	values[7]	values[3]	66	1			T283	14		T284	20		T285	24
auto[0]	values[7]	values[4]	104	1			T63	18		T286	12		T287	16
auto[0]	values[7]	values[5]	36	1			T67	8		T288	12		T289	8
auto[0]	values[7]	values[6]	26	1			T290	4		T291	22		-	-
auto[0]	values[7]	values[7]	76	1			T79	18		T292	32		T293	26
auto[1]	values[1]	values[5]	4	1			T202	4		-	-		-	-
auto[1]	values[3]	values[4]	2	1			T75	2		-	-		-	-
auto[1]	values[3]	values[6]	4	1			T65	4		-	-		-	-
auto[1]	values[4]	values[1]	2	1			T72	2		-	-		-	-
auto[1]	values[4]	values[7]	6	1			T245	6		-	-		-	-
auto[1]	values[5]	values[0]	2	1			T71	2		-	-		-	-
auto[1]	values[5]	values[2]	10	1			T294	10		-	-		-	-
auto[1]	values[5]	values[3]	2	1			T64	2		-	-		-	-
auto[1]	values[6]	values[3]	4	1			T74	2		T295	2		-	-
auto[1]	values[6]	values[4]	4	1			T70	4		-	-		-	-
auto[1]	values[6]	values[5]	2	1			T73	2		-	-		-	-
auto[1]	values[6]	values[6]	8	1			T4	8		-	-		-	-
auto[1]	values[7]	values[5]	2	1			T67	2		-	-		-	-