Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1505

1

T13

2

T14

9

T15

1

auto[1]

1527

1

T13

10

T14

9

T21

6

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

744

1

T15

1

T21

11

T22

27

auto[1]

2288

1

T13

12

T14

18

T23

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2775

1

T13

12

T14

18

T15

1

auto[1]

257

1

T21

5

T22

5

T59

7

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	626	1			T13	3		T14	3		T15	1
valid[1]	618	1			T13	2		T14	4		T21	3
valid[2]	625	1			T14	3		T21	3		T22	8
valid[3]	577	1			T13	2		T14	4		T21	2
valid[4]	586	1			T13	5		T14	4		T23	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	53	1			T15	1		T21	3		T22	2
auto[0]	auto[0]	valid[0]	auto[1]	245	1			T14	2		T21	1		T101	8
auto[0]	auto[0]	valid[1]	auto[0]	32	1			T22	1		T59	3		T61	1
auto[0]	auto[0]	valid[1]	auto[1]	237	1			T13	1		T14	2		T21	1
auto[0]	auto[0]	valid[2]	auto[0]	55	1			T22	5		T59	1		T61	3
auto[0]	auto[0]	valid[2]	auto[1]	231	1			T101	4		T102	5		T104	2
auto[0]	auto[0]	valid[3]	auto[0]	55	1			T22	3		T59	4		T61	3
auto[0]	auto[0]	valid[3]	auto[1]	210	1			T14	3		T101	7		T102	3
auto[0]	auto[0]	valid[4]	auto[0]	59	1			T22	5		T59	1		T61	2
auto[0]	auto[0]	valid[4]	auto[1]	202	1			T13	1		T14	2		T23	1
auto[0]	auto[1]	valid[0]	auto[0]	45	1			T21	1		T61	2		T390	1
auto[0]	auto[1]	valid[0]	auto[1]	228	1			T13	3		T14	1		T101	2
auto[0]	auto[1]	valid[1]	auto[0]	44	1			T21	1		T61	2		T391	1
auto[0]	auto[1]	valid[1]	auto[1]	254	1			T13	1		T14	2		T101	6
auto[0]	auto[1]	valid[2]	auto[0]	52	1			T22	2		T59	1		T61	4
auto[0]	auto[1]	valid[2]	auto[1]	228	1			T14	3		T21	1		T101	9
auto[0]	auto[1]	valid[3]	auto[0]	44	1			T21	1		T22	1		T59	1
auto[0]	auto[1]	valid[3]	auto[1]	229	1			T13	2		T14	1		T21	1
auto[0]	auto[1]	valid[4]	auto[0]	48	1			T22	3		T61	2		T103	3
auto[0]	auto[1]	valid[4]	auto[1]	224	1			T13	4		T14	2		T101	7
auto[1]	auto[0]	valid[0]	auto[0]	25	1			T21	1		T22	2		T61	2
auto[1]	auto[0]	valid[1]	auto[0]	24	1			T21	1		T61	2		T390	2
auto[1]	auto[0]	valid[2]	auto[0]	29	1			T21	2		T59	1		T61	1
auto[1]	auto[0]	valid[3]	auto[0]	20	1			T59	1		T391	2		T392	1
auto[1]	auto[0]	valid[4]	auto[0]	28	1			T59	2		T103	1		T406	1
auto[1]	auto[1]	valid[0]	auto[0]	30	1			T22	1		T61	2		T390	2
auto[1]	auto[1]	valid[1]	auto[0]	27	1			T59	2		T61	2		T103	1
auto[1]	auto[1]	valid[2]	auto[0]	30	1			T22	1		T59	1		T61	1
auto[1]	auto[1]	valid[3]	auto[0]	19	1			T22	1		T390	2		T100	1
auto[1]	auto[1]	valid[4]	auto[0]	25	1			T21	1		T61	2		T393	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal