Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18497

1

T3

6

T12

3

T15

8

auto[1]

21632

1

T13

12

T14

18

T23

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33543

1

T3

3

T12

2

T13

12

auto[1]

6586

1

T3

3

T12

1

T15

4

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	20848	1			T3	4		T13	12		T14	18
others[1]	3415	1			T3	1		T12	1		T21	27
others[2]	3305	1			T12	1		T21	34		T22	66
others[3]	3734	1			T3	1		T15	1		T20	1
interest[1]	2196	1			T12	1		T21	17		T22	40
interest[4]	13762	1			T3	4		T13	12		T14	18
interest[64]	6631	1			T15	3		T20	1		T21	48

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	6112	1			T3	1		T15	3		T20	2
auto[0]	auto[0]	others[1]	1026	1			T3	1		T21	15		T22	43
auto[0]	auto[0]	others[2]	984	1			T12	1		T21	18		T22	43
auto[0]	auto[0]	others[3]	1120	1			T3	1		T21	13		T22	43
auto[0]	auto[0]	interest[1]	647	1			T12	1		T21	9		T22	30
auto[0]	auto[0]	interest[4]	3968	1			T3	1		T15	2		T20	1
auto[0]	auto[0]	interest[64]	2022	1			T15	1		T21	30		T22	88
auto[0]	auto[1]	others[0]	11315	1			T13	12		T14	18		T23	1
auto[0]	auto[1]	others[1]	1810	1			T21	3		T101	64		T102	38
auto[0]	auto[1]	others[2]	1777	1			T21	5		T101	46		T102	33
auto[0]	auto[1]	others[3]	1980	1			T21	4		T101	52		T102	37
auto[0]	auto[1]	interest[1]	1217	1			T21	3		T101	29		T102	31
auto[0]	auto[1]	interest[4]	7538	1			T13	12		T14	18		T23	1
auto[0]	auto[1]	interest[64]	3533	1			T21	4		T101	113		T102	70
auto[1]	auto[0]	others[0]	3421	1			T3	3		T15	1		T20	2
auto[1]	auto[0]	others[1]	579	1			T12	1		T21	9		T22	17
auto[1]	auto[0]	others[2]	544	1			T21	11		T22	23		T59	14
auto[1]	auto[0]	others[3]	634	1			T15	1		T20	1		T21	10
auto[1]	auto[0]	interest[1]	332	1			T21	5		T22	10		T59	15
auto[1]	auto[0]	interest[4]	2256	1			T3	3		T20	2		T21	31
auto[1]	auto[0]	interest[64]	1076	1			T15	2		T20	1		T21	14

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal