Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	453	1			T32	10		T33	14		T34	14
all_values[1]	453	1			T32	10		T33	14		T34	14
all_values[2]	453	1			T32	10		T33	14		T34	14
all_values[3]	453	1			T32	10		T33	14		T34	14
all_values[4]	453	1			T32	10		T33	14		T34	14
all_values[5]	453	1			T32	10		T33	14		T34	14
all_values[6]	453	1			T32	10		T33	14		T34	14
all_values[7]	453	1			T32	10		T33	14		T34	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1903

1

T32

36

T33

52

T34

67

auto[1]

1721

1

T32

44

T33

60

T34

45

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1468

1

T32

26

T33

53

T34

56

auto[1]

2156

1

T32

54

T33

59

T34

56

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2073

1

T32

40

T33

68

T34

68

auto[1]

1551

1

T32

40

T33

44

T34

44

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	97	1			T32	1		T33	4		T34	6
all_values[0]	auto[0]	auto[0]	auto[1]	49	1			T40	1		T364	5		T365	2
all_values[0]	auto[0]	auto[1]	auto[0]	76	1			T32	1		T33	4		T34	2
all_values[0]	auto[0]	auto[1]	auto[1]	37	1			T32	3		T33	1		T34	1
all_values[0]	auto[1]	auto[0]	auto[1]	107	1			T32	3		T33	2		T34	2
all_values[0]	auto[1]	auto[1]	auto[1]	87	1			T32	2		T33	3		T34	3
all_values[1]	auto[0]	auto[0]	auto[0]	81	1			T32	3		T33	1		T34	5
all_values[1]	auto[0]	auto[0]	auto[1]	66	1			T32	1		T33	2		T34	2
all_values[1]	auto[0]	auto[1]	auto[0]	58	1			T32	2		T33	7		T34	2
all_values[1]	auto[0]	auto[1]	auto[1]	49	1			T40	4		T366	1		T365	1
all_values[1]	auto[1]	auto[0]	auto[1]	101	1			T32	2		T33	1		T34	4
all_values[1]	auto[1]	auto[1]	auto[1]	98	1			T32	2		T33	3		T34	1
all_values[2]	auto[0]	auto[0]	auto[0]	87	1			T32	3		T33	5		T34	2
all_values[2]	auto[0]	auto[0]	auto[1]	36	1			T33	1		T34	1		T40	2
all_values[2]	auto[0]	auto[1]	auto[0]	70	1			T33	1		T34	5		T366	1
all_values[2]	auto[0]	auto[1]	auto[1]	46	1			T33	1		T40	1		T367	1
all_values[2]	auto[1]	auto[0]	auto[1]	104	1			T32	2		T33	4		T34	3
all_values[2]	auto[1]	auto[1]	auto[1]	110	1			T32	5		T33	2		T34	3
all_values[3]	auto[0]	auto[0]	auto[0]	107	1			T32	1		T33	5		T34	2
all_values[3]	auto[0]	auto[0]	auto[1]	45	1			T34	4		T366	3		T365	1
all_values[3]	auto[0]	auto[1]	auto[0]	84	1			T32	3		T33	3		T34	2
all_values[3]	auto[0]	auto[1]	auto[1]	39	1			T32	1		T33	2		T40	1
all_values[3]	auto[1]	auto[0]	auto[1]	95	1			T32	1		T34	4		T367	1
all_values[3]	auto[1]	auto[1]	auto[1]	83	1			T32	4		T33	4		T34	2
all_values[4]	auto[0]	auto[0]	auto[0]	99	1			T32	2		T33	2		T34	5
all_values[4]	auto[0]	auto[0]	auto[1]	45	1			T33	2		T40	3		T366	2
all_values[4]	auto[0]	auto[1]	auto[0]	87	1			T32	2		T33	2		T34	3
all_values[4]	auto[0]	auto[1]	auto[1]	38	1			T32	3		T33	1		T366	1
all_values[4]	auto[1]	auto[0]	auto[1]	96	1			T33	4		T34	1		T40	3
all_values[4]	auto[1]	auto[1]	auto[1]	88	1			T32	3		T33	3		T34	5
all_values[5]	auto[0]	auto[0]	auto[0]	138	1			T32	3		T33	3		T34	5
all_values[5]	auto[0]	auto[1]	auto[0]	119	1			T32	3		T33	5		T34	5
all_values[5]	auto[1]	auto[0]	auto[1]	112	1			T32	2		T33	2		T34	3
all_values[5]	auto[1]	auto[1]	auto[1]	84	1			T32	2		T33	4		T34	1
all_values[6]	auto[0]	auto[0]	auto[0]	83	1			T32	1		T33	1		T34	3
all_values[6]	auto[0]	auto[0]	auto[1]	42	1			T32	1		T33	2		T34	2
all_values[6]	auto[0]	auto[1]	auto[0]	94	1			T33	5		T34	3		T40	6
all_values[6]	auto[0]	auto[1]	auto[1]	39	1			T32	2		T367	1		T366	1
all_values[6]	auto[1]	auto[0]	auto[1]	101	1			T32	4		T33	4		T34	6
all_values[6]	auto[1]	auto[1]	auto[1]	94	1			T32	2		T33	2		T40	2
all_values[7]	auto[0]	auto[0]	auto[0]	85	1			T33	2		T34	2		T40	2
all_values[7]	auto[0]	auto[0]	auto[1]	30	1			T32	2		T33	1		T40	1
all_values[7]	auto[0]	auto[1]	auto[0]	103	1			T32	1		T33	3		T34	4
all_values[7]	auto[0]	auto[1]	auto[1]	44	1			T32	1		T33	2		T34	2
all_values[7]	auto[1]	auto[0]	auto[1]	97	1			T32	4		T33	4		T34	5
all_values[7]	auto[1]	auto[1]	auto[1]	94	1			T32	2		T33	2		T34	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal