Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	279342	1			T1	119		T2	7504		T3	1
all_values[1]	279342	1			T1	119		T2	7504		T3	1
all_values[2]	279342	1			T1	119		T2	7504		T3	1
all_values[3]	279342	1			T1	119		T2	7504		T3	1
all_values[4]	279342	1			T1	119		T2	7504		T3	1
all_values[5]	279342	1			T1	119		T2	7504		T3	1
all_values[6]	279342	1			T1	119		T2	7504		T3	1
all_values[7]	279342	1			T1	119		T2	7504		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2232172

1

T1

952

T2

60032

T3

8

auto[1]

2564

1

T28

78

T36

103

T37

140

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2232504

1

T1

950

T2

60032

T3

8

auto[1]

2232

1

T1

2

T16

6

T52

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	278884	1			T1	119		T2	7504		T3	1
all_values[0]	auto[0]	auto[1]	128	1			T28	6		T36	2		T37	11
all_values[0]	auto[1]	auto[0]	179	1			T28	5		T36	11		T37	7
all_values[0]	auto[1]	auto[1]	151	1			T28	8		T36	8		T37	9
all_values[1]	auto[0]	auto[0]	278905	1			T1	119		T2	7504		T3	1
all_values[1]	auto[0]	auto[1]	129	1			T28	3		T36	8		T37	4
all_values[1]	auto[1]	auto[0]	190	1			T28	5		T36	7		T37	7
all_values[1]	auto[1]	auto[1]	118	1			T28	2		T37	12		T348	7
all_values[2]	auto[0]	auto[0]	278863	1			T1	119		T2	7504		T3	1
all_values[2]	auto[0]	auto[1]	134	1			T36	6		T37	4		T348	1
all_values[2]	auto[1]	auto[0]	208	1			T28	12		T36	9		T37	12
all_values[2]	auto[1]	auto[1]	137	1			T28	3		T36	8		T37	9
all_values[3]	auto[0]	auto[0]	278892	1			T1	119		T2	7504		T3	1
all_values[3]	auto[0]	auto[1]	149	1			T28	3		T36	1		T37	9
all_values[3]	auto[1]	auto[0]	180	1			T28	9		T36	8		T37	6
all_values[3]	auto[1]	auto[1]	121	1			T28	6		T36	4		T37	9
all_values[4]	auto[0]	auto[0]	278875	1			T1	119		T2	7504		T3	1
all_values[4]	auto[0]	auto[1]	143	1			T12	6		T28	3		T36	3
all_values[4]	auto[1]	auto[0]	206	1			T28	9		T36	9		T37	13
all_values[4]	auto[1]	auto[1]	118	1			T28	1		T36	4		T37	10
all_values[5]	auto[0]	auto[0]	278741	1			T1	117		T2	7504		T3	1
all_values[5]	auto[0]	auto[1]	296	1			T1	2		T16	6		T52	1
all_values[5]	auto[1]	auto[0]	189	1			T28	1		T36	8		T37	9
all_values[5]	auto[1]	auto[1]	116	1			T28	3		T36	4		T37	4
all_values[6]	auto[0]	auto[0]	278907	1			T1	119		T2	7504		T3	1
all_values[6]	auto[0]	auto[1]	138	1			T28	3		T36	7		T37	6
all_values[6]	auto[1]	auto[0]	176	1			T28	4		T36	7		T37	10
all_values[6]	auto[1]	auto[1]	121	1			T36	3		T37	4		T348	3
all_values[7]	auto[0]	auto[0]	278879	1			T1	119		T2	7504		T3	1
all_values[7]	auto[0]	auto[1]	109	1			T28	4		T36	4		T37	7
all_values[7]	auto[1]	auto[0]	230	1			T28	8		T36	11		T37	10
all_values[7]	auto[1]	auto[1]	124	1			T28	2		T36	2		T37	9