Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.69	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	25	59	70.24

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	23	25	52.08	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	1321	1			T3	14		T5	4		T8	6
auto[SpiFlashAddrCfg]	834	1			T5	10		T8	2		T10	4
auto[SpiFlashAddr3b]	1027	1			T4	2		T5	8		T6	9
auto[SpiFlashAddr4b]	845	1			T5	10		T7	4		T8	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3181

1

T3

14

T4

2

T5

32

auto[1]

846

1

T7

6

T11

26

T59

22

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2065

1

T3

2

T4

2

T5

18

auto[1]

1962

1

T3

12

T5

14

T6

9

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1705	1			T3	14		T5	10		T6	5
values[1]	66	1			T78	7		T59	2		T165	2
values[2]	200	1			T9	6		T42	6		T85	10
values[3]	187	1			T5	8		T10	4		T11	6
values[4]	179	1			T109	6		T162	2		T60	2
values[5]	151	1			T64	2		T65	4		T59	2
values[6]	182	1			T6	4		T9	2		T10	2
values[7]	190	1			T4	2		T5	4		T11	2
values[8]	1167	1			T5	10		T7	2		T8	4

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3486

1

T3

14

T4

2

T5

32

auto[1]

541

1

T6

9

T12

19

T78

14

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3919

1

T3

14

T4

2

T5

32

write

108

1

T7

4

T10

2

T11

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1749

1

T4

2

T5

30

T6

4

valids[0x1]

2278

1

T3

14

T5

2

T6

5

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	221	1			T3	4		T64	4		T39	6
internal_process_ops[0x5a]	202	1			T10	2		T42	6		T65	2
internal_process_ops[0x05]	269	1			T3	2		T5	2		T11	4
internal_process_ops[0x35]	243	1			T3	6		T8	4		T11	2
internal_process_ops[0x15]	244	1			T3	2		T59	2		T39	4
internal_process_ops[0x03]	192	1			T6	5		T78	5		T66	2
internal_process_ops[0x0b]	277	1			T78	2		T64	6		T90	2
internal_process_ops[0x3b]	265	1			T5	6		T9	2		T11	6
internal_process_ops[0x6b]	301	1			T12	6		T90	2		T84	4
internal_process_ops[0xbb]	248	1			T6	4		T8	2		T9	2
internal_process_ops[0xeb]	211	1			T4	2		T5	2		T12	5

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3974

1

T3

14

T4

2

T5

32

auto[1]

53

1

T7

4

T11

2

T60

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4027

1

T3

14

T4

2

T5

32

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	23	25	52.08	23
Automatically Generated Cross Bins	48	23	25	52.08	23
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[write]	[auto[SpiFlashAddrDisabled] , auto[SpiFlashAddrCfg]]	*	*	--	--	8
[auto[1]]	[write]	[auto[SpiFlashAddr3b]]	[auto[1]]	*	--	--	2
[auto[1]]	[write]	[auto[SpiFlashAddr4b]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[read]	[auto[SpiFlashAddr3b]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[write]	[auto[SpiFlashAddr3b]]	[auto[0]]	[auto[0]]	0	1	1
[auto[1]]	[write]	[auto[SpiFlashAddr4b]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	read	auto[SpiFlashAddrDisabled]	auto[0]	auto[0]	1052	1			T3	14		T5	4		T8	6
auto[0]	read	auto[SpiFlashAddrDisabled]	auto[1]	auto[0]	218	1			T11	6		T59	2		T51	2
auto[0]	read	auto[SpiFlashAddrCfg]	auto[0]	auto[0]	502	1			T5	10		T8	2		T10	4
auto[0]	read	auto[SpiFlashAddrCfg]	auto[1]	auto[0]	162	1			T11	6		T59	12		T60	2
auto[0]	read	auto[SpiFlashAddr3b]	auto[0]	auto[0]	602	1			T4	2		T5	8		T9	6
auto[0]	read	auto[SpiFlashAddr3b]	auto[1]	auto[0]	228	1			T11	2		T59	4		T66	6
auto[0]	read	auto[SpiFlashAddr4b]	auto[0]	auto[0]	436	1			T5	10		T8	2		T9	2
auto[0]	read	auto[SpiFlashAddr4b]	auto[1]	auto[0]	180	1			T7	2		T11	10		T59	4
auto[0]	write	auto[SpiFlashAddrDisabled]	auto[0]	auto[0]	30	1			T68	4		T228	8		T184	4
auto[0]	write	auto[SpiFlashAddrDisabled]	auto[1]	auto[1]	10	1			T11	2		T69	2		T279	4
auto[0]	write	auto[SpiFlashAddrCfg]	auto[0]	auto[0]	6	1			T62	2		T187	2		T328	2
auto[0]	write	auto[SpiFlashAddrCfg]	auto[1]	auto[1]	12	1			T63	4		T73	2		T74	2
auto[0]	write	auto[SpiFlashAddr3b]	auto[0]	auto[0]	12	1			T10	2		T67	2		T68	2
auto[0]	write	auto[SpiFlashAddr3b]	auto[1]	auto[1]	10	1			T7	2		T60	2		T73	4
auto[0]	write	auto[SpiFlashAddr4b]	auto[0]	auto[0]	6	1			T62	4		T329	2		-	-
auto[0]	write	auto[SpiFlashAddr4b]	auto[1]	auto[1]	20	1			T7	2		T70	4		T71	2
auto[1]	read	auto[SpiFlashAddrDisabled]	auto[0]	auto[0]	9	1			T330	3		T81	6		-	-
auto[1]	read	auto[SpiFlashAddrDisabled]	auto[1]	auto[0]	2	1			T81	2		-	-		-	-
auto[1]	read	auto[SpiFlashAddrCfg]	auto[0]	auto[0]	149	1			T12	13		T78	7		T141	7
auto[1]	read	auto[SpiFlashAddrCfg]	auto[1]	auto[0]	3	1			T81	3		-	-		-	-
auto[1]	read	auto[SpiFlashAddr3b]	auto[0]	auto[0]	174	1			T6	9		T78	7		T141	4
auto[1]	read	auto[SpiFlashAddr4b]	auto[0]	auto[0]	201	1			T12	6		T141	9		T331	2
auto[1]	read	auto[SpiFlashAddr4b]	auto[1]	auto[0]	1	1			T81	1		-	-		-	-
auto[1]	write	auto[SpiFlashAddr3b]	auto[0]	auto[1]	1	1			T81	1		-	-		-	-
auto[1]	write	auto[SpiFlashAddr4b]	auto[0]	auto[0]	1	1			T103	1		-	-		-	-

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	288	1			T5	8		T8	2		T59	2
auto[0]	values[0]	valids[0x1]	1366	1			T3	14		T5	2		T7	4
auto[0]	values[1]	valids[0x1]	48	1			T59	2		T165	2		T67	4
auto[0]	values[2]	valids[0x0]	102	1			T9	6		T85	10		T162	2
auto[0]	values[2]	valids[0x1]	56	1			T42	6		T68	2		T182	2
auto[0]	values[3]	valids[0x0]	102	1			T5	8		T10	4		T11	6
auto[0]	values[3]	valids[0x1]	52	1			T66	2		T268	8		T237	2
auto[0]	values[4]	valids[0x0]	96	1			T109	6		T162	2		T63	2
auto[0]	values[4]	valids[0x1]	50	1			T60	2		T263	2		T182	2
auto[0]	values[5]	valids[0x0]	100	1			T59	2		T60	2		T263	4
auto[0]	values[5]	valids[0x1]	34	1			T64	2		T65	4		T266	4
auto[0]	values[6]	valids[0x0]	60	1			T9	2		T69	4		T61	2
auto[0]	values[6]	valids[0x1]	60	1			T10	2		T66	4		T237	4
auto[0]	values[7]	valids[0x0]	122	1			T4	2		T5	4		T64	2
auto[0]	values[7]	valids[0x1]	44	1			T11	2		T263	2		T235	8
auto[0]	values[8]	valids[0x0]	536	1			T5	10		T7	2		T8	2
auto[0]	values[8]	valids[0x1]	370	1			T8	2		T59	2		T90	2
auto[1]	values[0]	valids[0x0]	5	1			T81	5		-	-		-	-
auto[1]	values[0]	valids[0x1]	46	1			T6	5		T331	2		T332	2
auto[1]	values[1]	valids[0x1]	18	1			T78	7		T330	3		T333	4
auto[1]	values[2]	valids[0x0]	35	1			T332	10		T334	5		T335	7
auto[1]	values[2]	valids[0x1]	7	1			T141	3		T332	4		-	-
auto[1]	values[3]	valids[0x0]	29	1			T331	12		T336	1		T337	10
auto[1]	values[3]	valids[0x1]	4	1			T336	4		-	-		-	-
auto[1]	values[4]	valids[0x0]	27	1			T103	8		T333	8		T338	3
auto[1]	values[4]	valids[0x1]	6	1			T339	4		T340	2		-	-
auto[1]	values[5]	valids[0x0]	9	1			T341	4		T342	5		-	-
auto[1]	values[5]	valids[0x1]	8	1			T343	1		T344	3		T345	4
auto[1]	values[6]	valids[0x0]	48	1			T6	4		T12	5		T332	2
auto[1]	values[6]	valids[0x1]	14	1			T334	3		T336	4		T335	4
auto[1]	values[7]	valids[0x0]	23	1			T78	5		T334	3		T346	2
auto[1]	values[7]	valids[0x1]	1	1			T81	1		-	-		-	-
auto[1]	values[8]	valids[0x0]	167	1			T12	14		T78	2		T141	13
auto[1]	values[8]	valids[0x1]	94	1			T141	4		T334	8		T103	3