Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2144771 1 T3 32342 T4 1 T5 3


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1980103 1 T3 32342 T4 1 T5 1
auto[1] 164668 1 T5 2 T8 6378 T39 21546


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 420105 1 T3 1543 T4 1 T5 3
auto[524288:1048575] 238606 1 T6 418 T12 44 T80 2914
auto[1048576:1572863] 304349 1 T3 15354 T6 1312 T12 28
auto[1572864:2097151] 268373 1 T3 8028 T6 1312 T12 142
auto[2097152:2621439] 254051 1 T3 1731 T6 3 T12 14
auto[2621440:3145727] 239797 1 T3 4884 T6 1086 T12 77
auto[3145728:3670015] 209650 1 T3 800 T6 179 T12 80
auto[3670016:4194303] 209840 1 T3 2 T6 273 T12 82


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 177468 1 T3 279 T4 1 T5 3
auto[1] 1967303 1 T3 32063 T6 5044 T12 508


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2144771 1 T3 32342 T4 1 T5 3


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 290987 1 T3 1543 T4 1 T5 1
auto[0] auto[0] auto[0:524287] auto[1] 129118 1 T5 2 T8 6378 T39 10971
auto[0] auto[0] auto[524288:1048575] auto[0] 234926 1 T6 418 T12 44 T80 2914
auto[0] auto[0] auto[524288:1048575] auto[1] 3680 1 T39 520 T85 212 T158 1
auto[0] auto[0] auto[1048576:1572863] auto[0] 301256 1 T3 15354 T6 1312 T12 28
auto[0] auto[0] auto[1048576:1572863] auto[1] 3093 1 T39 1221 T158 54 T159 1
auto[0] auto[0] auto[1572864:2097151] auto[0] 260432 1 T3 8028 T6 1312 T12 142
auto[0] auto[0] auto[1572864:2097151] auto[1] 7941 1 T39 1671 T159 758 T106 1028
auto[0] auto[0] auto[2097152:2621439] auto[0] 246044 1 T3 1731 T6 3 T12 14
auto[0] auto[0] auto[2097152:2621439] auto[1] 8007 1 T39 5792 T85 5 T158 85
auto[0] auto[0] auto[2621440:3145727] auto[0] 234674 1 T3 4884 T6 1086 T12 77
auto[0] auto[0] auto[2621440:3145727] auto[1] 5123 1 T39 4 T158 62 T159 2
auto[0] auto[0] auto[3145728:3670015] auto[0] 207536 1 T3 800 T6 179 T12 80
auto[0] auto[0] auto[3145728:3670015] auto[1] 2114 1 T39 1364 T158 221 T106 3
auto[0] auto[0] auto[3670016:4194303] auto[0] 204248 1 T3 2 T6 273 T12 82
auto[0] auto[0] auto[3670016:4194303] auto[1] 5592 1 T39 3 T85 1 T159 257


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 177468 1 T3 279 T4 1 T5 3
auto[0] auto[0] auto[1] 1967303 1 T3 32063 T6 5044 T12 508

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%