Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
77.40	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	33	95	74.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	33	95	74.22	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2646

1

T3

14

T4

2

T5

32

auto[1]

840

1

T7

6

T11

26

T59

22

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	508	1			T8	10		T65	10		T39	24
values[1]	424	1			T3	14		T59	22		T86	8
values[2]	484	1			T5	32		T11	26		T42	16
values[3]	374	1			T63	36		T263	18		T206	6
values[4]	396	1			T22	22		T163	14		T69	12
values[5]	510	1			T4	2		T7	6		T9	8
values[6]	342	1			T90	8		T109	14		T51	4
values[7]	448	1			T10	12		T80	2		T64	18

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	534	1			T11	26		T65	10		T23	8
values[1]	420	1			T109	14		T22	22		T156	22
values[2]	502	1			T4	2		T8	10		T42	16
values[3]	350	1			T9	8		T84	8		T86	8
values[4]	546	1			T64	18		T59	22		T90	8
values[5]	376	1			T10	12		T80	2		T263	18
values[6]	428	1			T5	32		T67	38		T206	6
values[7]	330	1			T3	14		T7	6		T51	4

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	33	95	74.22	33

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[3]]	[values[7]]	0	1	1
[auto[0]]	[values[4]]	[values[2] , values[3]]	--	--	2
[auto[0]]	[values[5]]	[values[7]]	0	1	1
[auto[1]]	[values[0]]	[values[1]]	0	1	1
[auto[1]]	[values[0]]	[values[3] , values[4]]	--	--	2
[auto[1]]	[values[1]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[1]]	[values[6]]	0	1	1
[auto[1]]	[values[2]]	[values[1]]	0	1	1
[auto[1]]	[values[2]]	[values[3]]	0	1	1
[auto[1]]	[values[2]]	[values[6] , values[7]]	--	--	2
[auto[1]]	[values[3]]	[values[3]]	0	1	1
[auto[1]]	[values[3]]	[values[5] , values[6] , values[7]]	--	--	3
[auto[1]]	[values[4]]	[values[4] , values[5] , values[6]]	--	--	3
[auto[1]]	[values[5]]	[values[1] , values[2] , values[3]]	--	--	3
[auto[1]]	[values[6]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[6]]	[values[4] , values[5] , values[6]]	--	--	3
[auto[1]]	[values[7]]	[values[2]]	0	1	1
[auto[1]]	[values[7]]	[values[5]]	0	1	1
[auto[1]]	[values[7]]	[values[7]]	0	1	1

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	64	1			T65	10		T23	8		T200	14
auto[0]	values[0]	values[1]	46	1			T156	22		T275	24		-	-
auto[0]	values[0]	values[2]	54	1			T8	10		T160	2		T68	20
auto[0]	values[0]	values[3]	38	1			T84	8		T276	30		-	-
auto[0]	values[0]	values[4]	32	1			T39	24		T188	8		-	-
auto[0]	values[0]	values[5]	34	1			T285	2		T273	18		T253	14
auto[0]	values[0]	values[6]	64	1			T266	34		T244	10		T258	20
auto[0]	values[0]	values[7]	60	1			T41	14		T233	16		T286	6
auto[0]	values[1]	values[0]	40	1			T96	2		T158	22		T287	16
auto[0]	values[1]	values[1]	40	1			T204	14		T192	24		T288	2
auto[0]	values[1]	values[2]	70	1			T289	8		T213	38		T225	4
auto[0]	values[1]	values[3]	38	1			T86	8		T205	24		T83	6
auto[0]	values[1]	values[4]	4	1			T290	4		-	-		-	-
auto[0]	values[1]	values[5]	72	1			T220	32		T181	2		T291	38
auto[0]	values[1]	values[6]	8	1			T292	8		-	-		-	-
auto[0]	values[1]	values[7]	88	1			T3	14		T75	8		T178	16
auto[0]	values[2]	values[0]	10	1			T82	2		T293	8		-	-
auto[0]	values[2]	values[1]	68	1			T197	32		T217	14		T272	4
auto[0]	values[2]	values[2]	124	1			T42	16		T40	12		T179	6
auto[0]	values[2]	values[3]	12	1			T268	8		T216	2		T294	2
auto[0]	values[2]	values[4]	70	1			T241	18		T252	22		T295	20
auto[0]	values[2]	values[5]	20	1			T189	6		T207	14		-	-
auto[0]	values[2]	values[6]	70	1			T5	32		T67	38		-	-
auto[0]	values[2]	values[7]	12	1			T296	12		-	-		-	-
auto[0]	values[3]	values[0]	16	1			T264	14		T243	2		-	-
auto[0]	values[3]	values[1]	32	1			T183	12		T297	20		-	-
auto[0]	values[3]	values[2]	4	1			T298	4		-	-		-	-
auto[0]	values[3]	values[3]	20	1			T88	4		T89	12		T175	4
auto[0]	values[3]	values[4]	18	1			T24	4		T105	4		T299	6
auto[0]	values[3]	values[5]	100	1			T263	18		T61	14		T228	30
auto[0]	values[3]	values[6]	80	1			T206	6		T270	18		T199	6
auto[0]	values[4]	values[0]	72	1			T163	14		T203	18		T247	30
auto[0]	values[4]	values[1]	90	1			T22	22		T238	8		T250	26
auto[0]	values[4]	values[4]	50	1			T62	32		T224	18		-	-
auto[0]	values[4]	values[5]	12	1			T267	12		-	-		-	-
auto[0]	values[4]	values[6]	30	1			T256	12		T300	6		T186	12
auto[0]	values[4]	values[7]	52	1			T226	10		T198	18		T301	4
auto[0]	values[5]	values[0]	96	1			T165	40		T159	12		T195	2
auto[0]	values[5]	values[1]	30	1			T193	4		T271	20		T302	6
auto[0]	values[5]	values[2]	28	1			T4	2		T161	12		T162	8
auto[0]	values[5]	values[3]	8	1			T9	8		-	-		-	-
auto[0]	values[5]	values[4]	62	1			T85	22		T106	40		-	-
auto[0]	values[5]	values[5]	8	1			T234	8		-	-		-	-
auto[0]	values[5]	values[6]	54	1			T208	16		T231	6		T303	14
auto[0]	values[6]	values[0]	38	1			T265	16		T240	4		T214	18
auto[0]	values[6]	values[1]	48	1			T109	14		T107	24		T304	6
auto[0]	values[6]	values[2]	12	1			T305	2		T306	10		-	-
auto[0]	values[6]	values[3]	84	1			T235	20		T218	16		T254	8
auto[0]	values[6]	values[4]	70	1			T90	8		T87	16		T245	8
auto[0]	values[6]	values[5]	14	1			T242	14		-	-		-	-
auto[0]	values[6]	values[6]	8	1			T196	4		T230	4		-	-
auto[0]	values[6]	values[7]	22	1			T176	12		T307	10		-	-
auto[0]	values[7]	values[0]	38	1			T76	8		T308	10		T255	20
auto[0]	values[7]	values[1]	22	1			T260	10		T251	10		T309	2
auto[0]	values[7]	values[2]	68	1			T211	18		T310	14		T168	36
auto[0]	values[7]	values[3]	82	1			T171	20		T232	12		T311	18
auto[0]	values[7]	values[4]	56	1			T64	18		T237	28		T312	10
auto[0]	values[7]	values[5]	46	1			T10	12		T80	2		T277	2
auto[0]	values[7]	values[6]	8	1			T313	8		-	-		-	-
auto[0]	values[7]	values[7]	30	1			T269	30		-	-		-	-
auto[1]	values[0]	values[0]	22	1			T70	16		T194	6		-	-
auto[1]	values[0]	values[2]	32	1			T239	32		-	-		-	-
auto[1]	values[0]	values[5]	26	1			T283	26		-	-		-	-
auto[1]	values[0]	values[6]	20	1			T314	20		-	-		-	-
auto[1]	values[0]	values[7]	16	1			T66	16		-	-		-	-
auto[1]	values[1]	values[3]	14	1			T172	12		T219	2		-	-
auto[1]	values[1]	values[4]	22	1			T59	22		-	-		-	-
auto[1]	values[1]	values[5]	24	1			T74	24		-	-		-	-
auto[1]	values[1]	values[7]	4	1			T167	4		-	-		-	-
auto[1]	values[2]	values[0]	40	1			T11	26		T279	14		-	-
auto[1]	values[2]	values[2]	12	1			T71	12		-	-		-	-
auto[1]	values[2]	values[4]	30	1			T315	30		-	-		-	-
auto[1]	values[2]	values[5]	16	1			T316	16		-	-		-	-
auto[1]	values[3]	values[0]	18	1			T236	6		T280	12		-	-
auto[1]	values[3]	values[1]	26	1			T248	18		T317	8		-	-
auto[1]	values[3]	values[2]	24	1			T282	24		-	-		-	-
auto[1]	values[3]	values[4]	36	1			T63	36		-	-		-	-
auto[1]	values[4]	values[0]	4	1			T318	4		-	-		-	-
auto[1]	values[4]	values[1]	12	1			T69	12		-	-		-	-
auto[1]	values[4]	values[2]	44	1			T190	16		T170	28		-	-
auto[1]	values[4]	values[3]	6	1			T209	6		-	-		-	-
auto[1]	values[4]	values[7]	24	1			T319	24		-	-		-	-
auto[1]	values[5]	values[0]	56	1			T164	22		T72	34		-	-
auto[1]	values[5]	values[4]	86	1			T182	20		T320	22		T321	14
auto[1]	values[5]	values[5]	4	1			T322	4		-	-		-	-
auto[1]	values[5]	values[6]	60	1			T323	18		T202	14		T324	28
auto[1]	values[5]	values[7]	18	1			T7	6		T60	12		-	-
auto[1]	values[6]	values[2]	30	1			T325	16		T284	14		-	-
auto[1]	values[6]	values[3]	12	1			T185	12		-	-		-	-
auto[1]	values[6]	values[7]	4	1			T51	4		-	-		-	-
auto[1]	values[7]	values[0]	20	1			T73	20		-	-		-	-
auto[1]	values[7]	values[1]	6	1			T261	6		-	-		-	-
auto[1]	values[7]	values[3]	36	1			T259	36		-	-		-	-
auto[1]	values[7]	values[4]	10	1			T326	8		T327	2		-	-
auto[1]	values[7]	values[6]	26	1			T223	26		-	-		-	-