Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.78	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	6	54	90.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	6	54	90.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	112	1			T84	4		T161	2		T85	10
auto[ReadAddrCrossIntoMailbox]	16	1			T161	4		T178	2		T193	2
auto[ReadAddrCrossOutOfMailbox]	16	1			T109	4		T161	2		T178	6
auto[ReadAddrCrossAllMailbox]	22	1			T109	4		T161	4		T178	6
auto[ReadAddrOutsideMailbox]	792	1			T4	2		T5	8		T8	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

479

1

T4

1

T5

4

T8

1

auto[1]

479

1

T4

1

T5

4

T8

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	118	1			T66	2		T165	2		T63	2
read_ops[0x0b]	168	1			T64	6		T90	2		T109	8
read_ops[0x3b]	180	1			T5	6		T9	2		T11	6
read_ops[0x6b]	176	1			T90	2		T84	4		T161	2
read_ops[0xbb]	186	1			T8	2		T9	2		T11	4
read_ops[0xeb]	130	1			T4	2		T5	2		T65	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	6	54	90.00	6

Automatically Generated Cross Bins for cr_all

Element holes

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	NUMBER	STATUS
[read_ops[0x03]]	[auto[ReadAddrCrossIntoMailbox]]	*	--	--	2
[read_ops[0x6b]]	[auto[ReadAddrCrossIntoMailbox] , auto[ReadAddrCrossOutOfMailbox]]	*	--	--	4

Covered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	10	1			T226	1		T179	1		T310	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	10	1			T226	1		T179	1		T310	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T178	1		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T178	1		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	1	1			T178	1		-	-		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	1	1			T178	1		-	-		-	-
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	47	1			T66	1		T165	1		T63	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	47	1			T66	1		T165	1		T63	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	8	1			T75	1		T159	3		T178	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	8	1			T75	1		T159	3		T178	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T178	1		T186	2		-	-
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T178	1		T186	2		-	-
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T109	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T109	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	1	1			T178	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	1	1			T178	1		-	-		-	-
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	71	1			T64	3		T90	1		T109	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	71	1			T64	3		T90	1		T109	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	15	1			T85	4		T158	1		T224	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	15	1			T85	4		T158	1		T224	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T193	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T193	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T178	1		T224	2		-	-
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T178	1		T224	2		-	-
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T178	1		T193	1		T347	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T178	1		T193	1		T347	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	67	1			T5	3		T9	1		T11	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	67	1			T5	3		T9	1		T11	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	11	1			T84	2		T211	1		T254	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	11	1			T84	2		T211	1		T254	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	1	1			T161	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	1	1			T161	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	76	1			T90	1		T85	1		T164	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	76	1			T90	1		T85	1		T164	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	8	1			T161	1		T85	1		T86	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	8	1			T161	1		T85	1		T86	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T347	1		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T347	1		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T178	1		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T178	1		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T161	1		T347	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T161	1		T347	1		-	-
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	81	1			T8	1		T9	1		T11	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	81	1			T8	1		T9	1		T11	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	4	1			T211	2		T224	1		T258	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	4	1			T211	2		T224	1		T258	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T161	2		T224	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T161	2		T224	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T109	1		T161	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T109	1		T161	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	2	1			T109	2		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	2	1			T109	2		-	-		-	-
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	54	1			T4	1		T5	1		T65	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	54	1			T4	1		T5	1		T65	1