Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	279342	1			T1	119		T2	7504		T3	1
all_pins[1]	279342	1			T1	119		T2	7504		T3	1
all_pins[2]	279342	1			T1	119		T2	7504		T3	1
all_pins[3]	279342	1			T1	119		T2	7504		T3	1
all_pins[4]	279342	1			T1	119		T2	7504		T3	1
all_pins[5]	279342	1			T1	119		T2	7504		T3	1
all_pins[6]	279342	1			T1	119		T2	7504		T3	1
all_pins[7]	279342	1			T1	119		T2	7504		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2233730	1			T1	952		T2	60032		T3	8
values[0x1]	1006	1			T28	25		T36	33		T37	66
transitions[0x0=>0x1]	742	1			T28	23		T36	28		T37	40
transitions[0x1=>0x0]	755	1			T28	23		T36	28		T37	40

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	279191	1			T1	119		T2	7504		T3	1
all_pins[0]	values[0x1]	151	1			T28	8		T36	8		T37	9
all_pins[0]	transitions[0x0=>0x1]	117	1			T28	8		T36	8		T37	4
all_pins[0]	transitions[0x1=>0x0]	84	1			T28	2		T37	7		T348	6
all_pins[1]	values[0x0]	279224	1			T1	119		T2	7504		T3	1
all_pins[1]	values[0x1]	118	1			T28	2		T37	12		T348	7
all_pins[1]	transitions[0x0=>0x1]	83	1			T28	2		T37	8		T348	3
all_pins[1]	transitions[0x1=>0x0]	102	1			T28	3		T36	8		T37	5
all_pins[2]	values[0x0]	279205	1			T1	119		T2	7504		T3	1
all_pins[2]	values[0x1]	137	1			T28	3		T36	8		T37	9
all_pins[2]	transitions[0x0=>0x1]	95	1			T28	3		T36	5		T37	4
all_pins[2]	transitions[0x1=>0x0]	79	1			T28	6		T36	1		T37	4
all_pins[3]	values[0x0]	279221	1			T1	119		T2	7504		T3	1
all_pins[3]	values[0x1]	121	1			T28	6		T36	4		T37	9
all_pins[3]	transitions[0x0=>0x1]	91	1			T28	5		T36	4		T37	6
all_pins[3]	transitions[0x1=>0x0]	88	1			T36	4		T37	7		T348	1
all_pins[4]	values[0x0]	279224	1			T1	119		T2	7504		T3	1
all_pins[4]	values[0x1]	118	1			T28	1		T36	4		T37	10
all_pins[4]	transitions[0x0=>0x1]	92	1			T28	1		T36	3		T37	7
all_pins[4]	transitions[0x1=>0x0]	90	1			T28	3		T36	3		T37	1
all_pins[5]	values[0x0]	279226	1			T1	119		T2	7504		T3	1
all_pins[5]	values[0x1]	116	1			T28	3		T36	4		T37	4
all_pins[5]	transitions[0x0=>0x1]	98	1			T28	3		T36	4		T37	3
all_pins[5]	transitions[0x1=>0x0]	103	1			T36	3		T37	3		T348	3
all_pins[6]	values[0x0]	279221	1			T1	119		T2	7504		T3	1
all_pins[6]	values[0x1]	121	1			T36	3		T37	4		T348	3
all_pins[6]	transitions[0x0=>0x1]	85	1			T36	3		T37	1		T348	2
all_pins[6]	transitions[0x1=>0x0]	88	1			T28	2		T36	2		T37	6
all_pins[7]	values[0x0]	279218	1			T1	119		T2	7504		T3	1
all_pins[7]	values[0x1]	124	1			T28	2		T36	2		T37	9
all_pins[7]	transitions[0x0=>0x1]	81	1			T28	1		T36	1		T37	7
all_pins[7]	transitions[0x1=>0x0]	121	1			T28	7		T36	7		T37	7