Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
64.38	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	52	76	59.38

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	52	76	59.38	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	432	1			T10	12		T64	18		T51	4
values[1]	320	1			T109	14		T85	22		T160	2
values[2]	560	1			T7	6		T11	26		T156	22
values[3]	426	1			T39	24		T84	8		T161	12
values[4]	368	1			T8	10		T65	10		T162	8
values[5]	454	1			T3	14		T80	2		T42	16
values[6]	376	1			T4	2		T22	22		T63	36
values[7]	550	1			T5	32		T9	8		T90	8

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	444	1			T42	16		T60	12		T156	22
values[1]	384	1			T3	14		T10	12		T80	2
values[2]	528	1			T4	2		T59	22		T163	14
values[3]	408	1			T5	32		T23	8		T164	22
values[4]	456	1			T65	10		T22	22		T84	8
values[5]	486	1			T7	6		T39	24		T165	40
values[6]	422	1			T9	8		T11	26		T109	14
values[7]	358	1			T8	10		T64	18		T86	8

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3434

1

T3

14

T4

2

T5

32

auto[1]

52

1

T7

4

T11

2

T60

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	52	76	59.38	52

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	8
[auto[1]]	[values[3]]	*	--	--	8
[auto[1]]	[values[5]]	*	--	--	8

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[values[3]]	0	1	1
[auto[1]]	[values[1]]	[values[1]]	0	1	1
[auto[1]]	[values[1]]	[values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	5
[auto[1]]	[values[2]]	[values[1] , values[2] , values[3]]	--	--	3
[auto[1]]	[values[2]]	[values[7]]	0	1	1
[auto[1]]	[values[4]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[4]]	[values[3] , values[4] , values[5] , values[6]]	--	--	4
[auto[1]]	[values[6]]	[values[2] , values[3] , values[4] , values[5] , values[6]]	--	--	5
[auto[1]]	[values[7]]	[values[1] , values[2] , values[3] , values[4]]	--	--	4
[auto[1]]	[values[7]]	[values[6] , values[7]]	--	--	2

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	6	1			T166	6		-	-		-	-
auto[0]	values[0]	values[1]	52	1			T10	12		T167	4		T168	36
auto[0]	values[0]	values[2]	76	1			T24	4		T169	12		T170	28
auto[0]	values[0]	values[4]	64	1			T171	20		T172	12		T173	20
auto[0]	values[0]	values[5]	56	1			T165	40		T174	12		T175	4
auto[0]	values[0]	values[6]	94	1			T51	4		T176	12		T177	20
auto[0]	values[0]	values[7]	84	1			T64	18		T86	8		T178	16
auto[0]	values[1]	values[0]	60	1			T179	6		T180	24		T181	2
auto[0]	values[1]	values[1]	14	1			T41	14		-	-		-	-
auto[0]	values[1]	values[2]	72	1			T182	20		T183	12		T184	20
auto[0]	values[1]	values[3]	50	1			T185	12		T186	12		T187	24
auto[0]	values[1]	values[4]	36	1			T85	22		T188	8		T189	6
auto[0]	values[1]	values[5]	34	1			T89	12		T190	16		T191	6
auto[0]	values[1]	values[6]	38	1			T109	14		T192	24		-	-
auto[0]	values[1]	values[7]	10	1			T160	2		T75	8		-	-
auto[0]	values[2]	values[0]	78	1			T156	22		T96	2		T70	12
auto[0]	values[2]	values[1]	46	1			T193	4		T194	6		T82	2
auto[0]	values[2]	values[2]	90	1			T195	2		T107	24		T196	4
auto[0]	values[2]	values[3]	56	1			T197	32		T198	18		T199	6
auto[0]	values[2]	values[4]	64	1			T200	14		T201	8		T202	14
auto[0]	values[2]	values[5]	56	1			T7	2		T203	18		T204	14
auto[0]	values[2]	values[6]	96	1			T11	24		T71	10		T205	24
auto[0]	values[2]	values[7]	60	1			T206	6		T106	40		T207	14
auto[0]	values[3]	values[0]	42	1			T208	16		T209	6		T210	20
auto[0]	values[3]	values[1]	58	1			T68	20		T211	18		T212	12
auto[0]	values[3]	values[2]	66	1			T213	38		T214	18		T215	10
auto[0]	values[3]	values[3]	62	1			T216	2		T217	14		T218	16
auto[0]	values[3]	values[4]	44	1			T84	8		T161	12		T66	16
auto[0]	values[3]	values[5]	80	1			T39	24		T67	38		T219	2
auto[0]	values[3]	values[6]	32	1			T220	32		-	-		-	-
auto[0]	values[3]	values[7]	42	1			T221	2		T222	14		T223	26
auto[0]	values[4]	values[0]	44	1			T61	14		T224	18		T225	4
auto[0]	values[4]	values[1]	14	1			T226	10		T227	4		-	-
auto[0]	values[4]	values[2]	42	1			T228	30		T73	8		T229	4
auto[0]	values[4]	values[3]	4	1			T230	4		-	-		-	-
auto[0]	values[4]	values[4]	98	1			T65	10		T162	8		T83	6
auto[0]	values[4]	values[5]	40	1			T159	12		T231	6		T232	12
auto[0]	values[4]	values[6]	24	1			T233	16		T234	8		-	-
auto[0]	values[4]	values[7]	88	1			T8	10		T235	20		T236	6
auto[0]	values[5]	values[0]	72	1			T42	16		T237	28		T238	8
auto[0]	values[5]	values[1]	62	1			T3	14		T80	2		T158	22
auto[0]	values[5]	values[2]	58	1			T59	22		T239	32		T240	4
auto[0]	values[5]	values[3]	104	1			T23	8		T164	22		T241	18
auto[0]	values[5]	values[4]	34	1			T242	14		T243	2		T77	18
auto[0]	values[5]	values[5]	76	1			T244	10		T245	8		T246	32
auto[0]	values[5]	values[6]	30	1			T247	30		-	-		-	-
auto[0]	values[5]	values[7]	18	1			T248	18		-	-		-	-
auto[0]	values[6]	values[0]	44	1			T69	10		T72	30		T249	4
auto[0]	values[6]	values[1]	58	1			T74	22		T250	26		T251	10
auto[0]	values[6]	values[2]	42	1			T4	2		T252	22		T253	14
auto[0]	values[6]	values[3]	32	1			T62	32		-	-		-	-
auto[0]	values[6]	values[4]	52	1			T22	22		T254	8		T255	20
auto[0]	values[6]	values[5]	38	1			T256	12		T257	2		T258	20
auto[0]	values[6]	values[6]	56	1			T259	36		T260	10		T261	6
auto[0]	values[6]	values[7]	42	1			T63	32		T262	10		-	-
auto[0]	values[7]	values[0]	80	1			T60	10		T263	18		T264	14
auto[0]	values[7]	values[1]	78	1			T90	8		T40	12		T265	16
auto[0]	values[7]	values[2]	68	1			T163	14		T266	34		T267	12
auto[0]	values[7]	values[3]	100	1			T5	32		T268	8		T269	30
auto[0]	values[7]	values[4]	62	1			T270	18		T271	20		T272	4
auto[0]	values[7]	values[5]	100	1			T273	18		T274	14		T275	24
auto[0]	values[7]	values[6]	48	1			T9	8		T88	4		T276	30
auto[0]	values[7]	values[7]	8	1			T277	2		T278	6		-	-
auto[1]	values[1]	values[0]	4	1			T279	4		-	-		-	-
auto[1]	values[1]	values[2]	2	1			T280	2		-	-		-	-
auto[1]	values[2]	values[0]	4	1			T70	4		-	-		-	-
auto[1]	values[2]	values[4]	2	1			T281	2		-	-		-	-
auto[1]	values[2]	values[5]	4	1			T7	4		-	-		-	-
auto[1]	values[2]	values[6]	4	1			T11	2		T71	2		-	-
auto[1]	values[4]	values[2]	12	1			T73	12		-	-		-	-
auto[1]	values[4]	values[7]	2	1			T282	2		-	-		-	-
auto[1]	values[6]	values[0]	6	1			T69	2		T72	4		-	-
auto[1]	values[6]	values[1]	2	1			T74	2		-	-		-	-
auto[1]	values[6]	values[7]	4	1			T63	4		-	-		-	-
auto[1]	values[7]	values[0]	4	1			T60	2		T283	2		-	-
auto[1]	values[7]	values[5]	2	1			T284	2		-	-		-	-