Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1449

1

T2

10

T13

22

T14

24

auto[1]

1394

1

T2

5

T13

26

T14

37

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

699

1

T2

12

T16

1

T19

24

auto[1]

2144

1

T2

3

T13

48

T14

61

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2562

1

T2

10

T13

48

T14

61

auto[1]

281

1

T2

5

T19

10

T20

8

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	562	1			T2	2		T13	11		T14	18
valid[1]	562	1			T2	1		T13	11		T14	15
valid[2]	607	1			T2	8		T13	12		T14	9
valid[3]	567	1			T2	2		T13	7		T14	8
valid[4]	545	1			T2	2		T13	7		T14	11

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	47	1			T2	1		T19	1		T20	4
auto[0]	auto[0]	valid[0]	auto[1]	203	1			T13	5		T14	5		T15	4
auto[0]	auto[0]	valid[1]	auto[0]	46	1			T2	1		T19	2		T20	1
auto[0]	auto[0]	valid[1]	auto[1]	213	1			T13	5		T14	5		T15	6
auto[0]	auto[0]	valid[2]	auto[0]	49	1			T2	5		T19	2		T55	2
auto[0]	auto[0]	valid[2]	auto[1]	220	1			T13	4		T14	6		T15	1
auto[0]	auto[0]	valid[3]	auto[0]	52	1			T19	3		T20	1		T56	1
auto[0]	auto[0]	valid[3]	auto[1]	220	1			T13	3		T14	4		T15	6
auto[0]	auto[0]	valid[4]	auto[0]	39	1			T16	1		T19	2		T55	3
auto[0]	auto[0]	valid[4]	auto[1]	208	1			T13	5		T14	4		T15	6
auto[0]	auto[1]	valid[0]	auto[0]	44	1			T19	2		T54	1		T55	1
auto[0]	auto[1]	valid[0]	auto[1]	209	1			T13	6		T14	13		T15	3
auto[0]	auto[1]	valid[1]	auto[0]	39	1			T20	1		T55	4		T379	1
auto[0]	auto[1]	valid[1]	auto[1]	208	1			T13	6		T14	10		T15	7
auto[0]	auto[1]	valid[2]	auto[0]	36	1			T19	1		T54	1		T379	2
auto[0]	auto[1]	valid[2]	auto[1]	243	1			T2	1		T13	8		T14	3
auto[0]	auto[1]	valid[3]	auto[0]	30	1			T20	2		T55	1		T56	1
auto[0]	auto[1]	valid[3]	auto[1]	207	1			T2	1		T13	4		T14	4
auto[0]	auto[1]	valid[4]	auto[0]	36	1			T19	1		T55	1		T97	1
auto[0]	auto[1]	valid[4]	auto[1]	213	1			T2	1		T13	2		T14	7
auto[1]	auto[0]	valid[0]	auto[0]	34	1			T2	1		T19	1		T20	1
auto[1]	auto[0]	valid[1]	auto[0]	30	1			T19	1		T54	1		T56	1
auto[1]	auto[0]	valid[2]	auto[0]	33	1			T2	1		T55	2		T58	1
auto[1]	auto[0]	valid[3]	auto[0]	31	1			T19	1		T20	2		T55	1
auto[1]	auto[0]	valid[4]	auto[0]	24	1			T2	1		T19	1		T54	1
auto[1]	auto[1]	valid[0]	auto[0]	25	1			T55	2		T99	1		T382	1
auto[1]	auto[1]	valid[1]	auto[0]	26	1			T19	1		T20	1		T55	2
auto[1]	auto[1]	valid[2]	auto[0]	26	1			T2	1		T19	1		T55	1
auto[1]	auto[1]	valid[3]	auto[0]	27	1			T2	1		T19	2		T20	2
auto[1]	auto[1]	valid[4]	auto[0]	25	1			T19	2		T20	2		T55	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal