Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17623

1

T1

7

T2

338

T16

11

auto[1]

20891

1

T2

42

T13

630

T14

625

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32006

1

T1

4

T2

259

T13

630

auto[1]

6508

1

T1

3

T2

121

T16

8

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	19914	1			T1	3		T2	197		T13	328
others[1]	3100	1			T2	29		T13	46		T14	45
others[2]	3245	1			T1	1		T2	35		T13	49
others[3]	3718	1			T2	42		T13	73		T14	69
interest[1]	2114	1			T1	1		T2	21		T13	32
interest[4]	13082	1			T1	2		T2	121		T13	215
interest[64]	6423	1			T1	2		T2	56		T13	102

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	5624	1			T1	1		T2	115		T16	2
auto[0]	auto[0]	others[1]	953	1			T2	15		T19	22		T20	22
auto[0]	auto[0]	others[2]	949	1			T1	1		T2	20		T16	1
auto[0]	auto[0]	others[3]	1107	1			T2	24		T19	30		T20	23
auto[0]	auto[0]	interest[1]	617	1			T1	1		T2	10		T19	13
auto[0]	auto[0]	interest[4]	3631	1			T1	1		T2	65		T16	2
auto[0]	auto[0]	interest[64]	1865	1			T1	1		T2	33		T19	57
auto[0]	auto[1]	others[0]	10924	1			T2	24		T13	328		T14	316
auto[0]	auto[1]	others[1]	1638	1			T2	1		T13	46		T14	45
auto[0]	auto[1]	others[2]	1735	1			T2	4		T13	49		T14	64
auto[0]	auto[1]	others[3]	2002	1			T13	73		T14	69		T15	73
auto[0]	auto[1]	interest[1]	1117	1			T2	5		T13	32		T14	25
auto[0]	auto[1]	interest[4]	7284	1			T2	16		T13	215		T14	214
auto[0]	auto[1]	interest[64]	3475	1			T2	8		T13	102		T14	106
auto[1]	auto[0]	others[0]	3366	1			T1	2		T2	58		T16	5
auto[1]	auto[0]	others[1]	509	1			T2	13		T19	19		T20	11
auto[1]	auto[0]	others[2]	561	1			T2	11		T16	1		T19	11
auto[1]	auto[0]	others[3]	609	1			T2	18		T16	1		T19	13
auto[1]	auto[0]	interest[1]	380	1			T2	6		T19	4		T20	14
auto[1]	auto[0]	interest[4]	2167	1			T1	1		T2	40		T16	4
auto[1]	auto[0]	interest[64]	1083	1			T1	1		T2	15		T16	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal