Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	549	1			T28	18		T36	21		T37	27
all_values[1]	549	1			T28	18		T36	21		T37	27
all_values[2]	549	1			T28	18		T36	21		T37	27
all_values[3]	549	1			T28	18		T36	21		T37	27
all_values[4]	549	1			T28	18		T36	21		T37	27
all_values[5]	549	1			T28	18		T36	21		T37	27
all_values[6]	549	1			T28	18		T36	21		T37	27
all_values[7]	549	1			T28	18		T36	21		T37	27

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2289

1

T28

80

T36

86

T37

107

auto[1]

2103

1

T28

64

T36

82

T37

109

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1726

1

T28

66

T36

74

T37

72

auto[1]

2666

1

T28

78

T36

94

T37

144

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2495

1

T28

84

T36

100

T37

121

auto[1]

1897

1

T28

60

T36

68

T37

95

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	105	1			T28	1		T36	4		T37	1
all_values[0]	auto[0]	auto[0]	auto[1]	60	1			T28	5		T36	1		T37	6
all_values[0]	auto[0]	auto[1]	auto[0]	70	1			T28	2		T36	4		T37	3
all_values[0]	auto[0]	auto[1]	auto[1]	72	1			T28	3		T36	4		T37	3
all_values[0]	auto[1]	auto[0]	auto[1]	112	1			T28	2		T36	1		T37	7
all_values[0]	auto[1]	auto[1]	auto[1]	130	1			T28	5		T36	7		T37	7
all_values[1]	auto[0]	auto[0]	auto[0]	130	1			T28	9		T36	6		T37	6
all_values[1]	auto[0]	auto[0]	auto[1]	60	1			T28	1		T36	4		T37	4
all_values[1]	auto[0]	auto[1]	auto[0]	86	1			T28	2		T36	4		T348	3
all_values[1]	auto[0]	auto[1]	auto[1]	45	1			T28	1		T37	5		T348	3
all_values[1]	auto[1]	auto[0]	auto[1]	124	1			T28	2		T36	6		T37	7
all_values[1]	auto[1]	auto[1]	auto[1]	104	1			T28	3		T36	1		T37	5
all_values[2]	auto[0]	auto[0]	auto[0]	82	1			T28	3		T36	1		T37	3
all_values[2]	auto[0]	auto[0]	auto[1]	51	1			T36	1		T37	1		T150	2
all_values[2]	auto[0]	auto[1]	auto[0]	99	1			T28	9		T36	3		T37	5
all_values[2]	auto[0]	auto[1]	auto[1]	65	1			T28	1		T36	5		T37	4
all_values[2]	auto[1]	auto[0]	auto[1]	126	1			T28	1		T36	6		T37	6
all_values[2]	auto[1]	auto[1]	auto[1]	126	1			T28	4		T36	5		T37	8
all_values[3]	auto[0]	auto[0]	auto[0]	112	1			T28	3		T36	4		T37	1
all_values[3]	auto[0]	auto[0]	auto[1]	56	1			T36	1		T37	5		T150	1
all_values[3]	auto[0]	auto[1]	auto[0]	89	1			T28	2		T36	5		T37	4
all_values[3]	auto[0]	auto[1]	auto[1]	55	1			T28	3		T36	1		T37	2
all_values[3]	auto[1]	auto[0]	auto[1]	123	1			T28	6		T36	4		T37	6
all_values[3]	auto[1]	auto[1]	auto[1]	114	1			T28	4		T36	6		T37	9
all_values[4]	auto[0]	auto[0]	auto[0]	97	1			T28	4		T36	6		T37	4
all_values[4]	auto[0]	auto[0]	auto[1]	56	1			T28	1		T36	2		T37	2
all_values[4]	auto[0]	auto[1]	auto[0]	109	1			T28	4		T36	4		T37	6
all_values[4]	auto[0]	auto[1]	auto[1]	55	1			T28	1		T36	3		T37	9
all_values[4]	auto[1]	auto[0]	auto[1]	126	1			T28	5		T36	3		T37	5
all_values[4]	auto[1]	auto[1]	auto[1]	106	1			T28	3		T36	3		T37	1
all_values[5]	auto[0]	auto[0]	auto[0]	173	1			T28	7		T36	5		T37	11
all_values[5]	auto[0]	auto[1]	auto[0]	147	1			T28	3		T36	7		T37	8
all_values[5]	auto[1]	auto[0]	auto[1]	109	1			T28	5		T36	5		T37	6
all_values[5]	auto[1]	auto[1]	auto[1]	120	1			T28	3		T36	4		T37	2
all_values[6]	auto[0]	auto[0]	auto[0]	123	1			T28	8		T36	5		T37	7
all_values[6]	auto[0]	auto[0]	auto[1]	58	1			T28	1		T36	1		T37	2
all_values[6]	auto[0]	auto[1]	auto[0]	80	1			T28	1		T36	4		T37	5
all_values[6]	auto[0]	auto[1]	auto[1]	47	1			T37	2		T150	1		T349	3
all_values[6]	auto[1]	auto[0]	auto[1]	127	1			T28	6		T36	6		T37	7
all_values[6]	auto[1]	auto[1]	auto[1]	114	1			T28	2		T36	5		T37	4
all_values[7]	auto[0]	auto[0]	auto[0]	115	1			T28	3		T36	9		T37	2
all_values[7]	auto[0]	auto[0]	auto[1]	45	1			T28	1		T36	2		T37	2
all_values[7]	auto[0]	auto[1]	auto[0]	109	1			T28	5		T36	3		T37	6
all_values[7]	auto[0]	auto[1]	auto[1]	44	1			T36	1		T37	2		T348	3
all_values[7]	auto[1]	auto[0]	auto[1]	119	1			T28	6		T36	3		T37	6
all_values[7]	auto[1]	auto[1]	auto[1]	117	1			T28	3		T36	3		T37	9

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal