Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	282127	1			T1	1		T2	1		T4	1
all_values[1]	282127	1			T1	1		T2	1		T4	1
all_values[2]	282127	1			T1	1		T2	1		T4	1
all_values[3]	282127	1			T1	1		T2	1		T4	1
all_values[4]	282127	1			T1	1		T2	1		T4	1
all_values[5]	282127	1			T1	1		T2	1		T4	1
all_values[6]	282127	1			T1	1		T2	1		T4	1
all_values[7]	282127	1			T1	1		T2	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2255029

1

T1

8

T2

8

T4

8

auto[1]

1987

1

T19

82

T39

97

T41

23

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2255160

1

T1

8

T2

8

T4

8

auto[1]

1856

1

T19

75

T17

2

T48

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	281793	1			T1	1		T2	1		T4	1
all_values[0]	auto[0]	auto[1]	95	1			T19	5		T39	4		T41	3
all_values[0]	auto[1]	auto[0]	135	1			T19	6		T39	4		T41	1
all_values[0]	auto[1]	auto[1]	104	1			T19	5		T39	6		T40	3
all_values[1]	auto[0]	auto[0]	281758	1			T1	1		T2	1		T4	1
all_values[1]	auto[0]	auto[1]	107	1			T19	4		T39	4		T41	2
all_values[1]	auto[1]	auto[0]	157	1			T19	8		T39	8		T40	8
all_values[1]	auto[1]	auto[1]	105	1			T19	6		T39	2		T41	1
all_values[2]	auto[0]	auto[0]	281789	1			T1	1		T2	1		T4	1
all_values[2]	auto[0]	auto[1]	109	1			T19	4		T39	3		T40	7
all_values[2]	auto[1]	auto[0]	132	1			T19	4		T39	3		T41	4
all_values[2]	auto[1]	auto[1]	97	1			T19	4		T39	6		T41	2
all_values[3]	auto[0]	auto[0]	281724	1			T1	1		T2	1		T4	1
all_values[3]	auto[0]	auto[1]	137	1			T19	5		T39	4		T41	1
all_values[3]	auto[1]	auto[0]	161	1			T19	2		T39	7		T41	5
all_values[3]	auto[1]	auto[1]	105	1			T19	5		T39	3		T40	8
all_values[4]	auto[0]	auto[0]	281753	1			T1	1		T2	1		T4	1
all_values[4]	auto[0]	auto[1]	133	1			T19	6		T145	6		T39	1
all_values[4]	auto[1]	auto[0]	143	1			T19	2		T39	11		T41	2
all_values[4]	auto[1]	auto[1]	98	1			T19	4		T39	5		T41	3
all_values[5]	auto[0]	auto[0]	281563	1			T1	1		T2	1		T4	1
all_values[5]	auto[0]	auto[1]	296	1			T19	8		T17	2		T48	1
all_values[5]	auto[1]	auto[0]	174	1			T19	8		T39	9		T40	11
all_values[5]	auto[1]	auto[1]	94	1			T19	1		T39	5		T40	5
all_values[6]	auto[0]	auto[0]	281792	1			T1	1		T2	1		T4	1
all_values[6]	auto[0]	auto[1]	99	1			T19	3		T39	2		T40	7
all_values[6]	auto[1]	auto[0]	128	1			T19	3		T39	8		T41	4
all_values[6]	auto[1]	auto[1]	108	1			T19	9		T39	6		T40	2
all_values[7]	auto[0]	auto[0]	281800	1			T1	1		T2	1		T4	1
all_values[7]	auto[0]	auto[1]	81	1			T19	3		T39	1		T40	3
all_values[7]	auto[1]	auto[0]	158	1			T19	12		T39	10		T41	1
all_values[7]	auto[1]	auto[1]	88	1			T19	3		T39	4		T40	1