Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
72.13	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	33	51	60.71

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	29	19	39.58	100	1	1	0
cr_modeXdummyXnum_lanes	36	4	32	88.89	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	1210	1			T6	4		T8	14		T9	14
auto[SpiFlashAddrCfg]	879	1			T4	4		T5	6		T6	12
auto[SpiFlashAddr3b]	942	1			T2	4		T6	8		T8	8
auto[SpiFlashAddr4b]	834	1			T5	10		T6	6		T8	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2979

1

T2

4

T4

4

T5

16

auto[1]

886

1

T6

30

T56

18

T57

16

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1925

1

T2

4

T4

2

T5

2

auto[1]

1940

1

T4

2

T5

14

T6

8

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1531	1			T2	2		T4	2		T6	16
values[1]	85	1			T18	2		T43	2		T59	8
values[2]	180	1			T2	2		T8	8		T56	4
values[3]	179	1			T43	2		T60	6		T28	2
values[4]	206	1			T86	2		T161	2		T62	4
values[5]	201	1			T4	2		T8	2		T198	6
values[6]	137	1			T6	8		T160	2		T148	4
values[7]	147	1			T5	12		T8	2		T234	2
values[8]	1199	1			T5	4		T6	6		T8	6

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3308

1

T2

4

T4

4

T5

16

auto[1]

557

1

T145

9

T148

11

T151

10

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3735

1

T2

2

T4

4

T5

16

write

130

1

T2

2

T6

6

T56

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1792

1

T2

2

T4

2

T5

12

valids[0x1]

2073

1

T2

2

T4

2

T5

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	188	1			T6	2		T8	2		T9	4
internal_process_ops[0x5a]	142	1			T9	2		T18	2		T43	2
internal_process_ops[0x05]	214	1			T6	2		T11	6		T18	4
internal_process_ops[0x35]	216	1			T8	4		T94	6		T129	2
internal_process_ops[0x15]	194	1			T8	4		T9	10		T43	4
internal_process_ops[0x03]	261	1			T4	2		T5	4		T8	2
internal_process_ops[0x0b]	230	1			T6	4		T8	2		T18	2
internal_process_ops[0x3b]	279	1			T6	6		T18	2		T84	2
internal_process_ops[0x6b]	242	1			T5	10		T18	2		T56	4
internal_process_ops[0xbb]	295	1			T8	4		T43	2		T145	6
internal_process_ops[0xeb]	276	1			T4	2		T5	2		T6	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3801

1

T2

4

T4

4

T5

16

auto[1]

64

1

T6

6

T56

2

T58

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3865

1

T2

4

T4

4

T5

16

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	29	19	39.58	29
Automatically Generated Cross Bins	48	29	19	39.58	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[read]	[auto[SpiFlashAddrDisabled]]	*	[auto[0]]	--	--	2
[auto[1]]	[write]	*	*	*	--	--	16

Uncovered bins

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[read]	[auto[SpiFlashAddrCfg] , auto[SpiFlashAddr3b] , auto[SpiFlashAddr4b]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

946

1

T8

14

T9

14

T10

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

228

1

T6

4

T57

12

T58

10

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

480

1

T4

4

T5

6

T8

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

222

1

T6

12

T56

4

T234

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

544

1

T2

2

T8

8

T9

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

198

1

T6

8

T56

8

T57

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

386

1

T5

10

T8

6

T59

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

174

1

T56

4

T57

2

T234

10

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

16

1

T60

2

T160

4

T27

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

20

1

T64

2

T66

2

T69

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

12

1

T160

2

T226

2

T221

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

18

1

T58

4

T65

4

T67

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

12

1

T2

2

T201

2

T275

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

4

1

T69

4

-

-

-

-

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

26

1

T59

6

T204

2

T191

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

22

1

T6

6

T56

2

T58

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

147

1

T145

6

T148

4

T75

8

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

184

1

T145

1

T148

2

T151

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

226

1

T145

2

T148

5

T151

8

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	4	32	88.89	4

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[2]]	[valids[0x1]]	0	1	1
[auto[1]]	[values[5]]	[valids[0x1]]	0	1	1

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	272	1			T6	2		T8	4		T10	2
auto[0]	values[0]	valids[0x1]	1214	1			T2	2		T4	2		T6	14
auto[0]	values[1]	valids[0x1]	74	1			T18	2		T43	2		T59	8
auto[0]	values[2]	valids[0x0]	114	1			T2	2		T8	4		T198	2
auto[0]	values[2]	valids[0x1]	50	1			T8	4		T56	4		T156	2
auto[0]	values[3]	valids[0x0]	94	1			T60	4		T61	8		T204	6
auto[0]	values[3]	valids[0x1]	46	1			T43	2		T60	2		T28	2
auto[0]	values[4]	valids[0x0]	90	1			T86	2		T62	4		T85	10
auto[0]	values[4]	valids[0x1]	50	1			T161	2		T57	2		T87	2
auto[0]	values[5]	valids[0x0]	118	1			T4	2		T8	2		T198	6
auto[0]	values[5]	valids[0x1]	50	1			T244	6		T156	4		T211	2
auto[0]	values[6]	valids[0x0]	82	1			T6	8		T25	4		T162	6
auto[0]	values[6]	valids[0x1]	8	1			T160	2		T63	2		T276	2
auto[0]	values[7]	valids[0x0]	76	1			T5	12		T234	2		T70	2
auto[0]	values[7]	valids[0x1]	52	1			T8	2		T228	6		T176	6
auto[0]	values[8]	valids[0x0]	564	1			T6	6		T8	4		T18	8
auto[0]	values[8]	valids[0x1]	354	1			T5	4		T8	2		T9	2
auto[1]	values[0]	valids[0x0]	4	1			T76	4		-	-		-	-
auto[1]	values[0]	valids[0x1]	41	1			T151	2		T277	2		T278	6
auto[1]	values[1]	valids[0x1]	11	1			T279	5		T280	2		T281	4
auto[1]	values[2]	valids[0x0]	16	1			T282	6		T283	2		T284	7
auto[1]	values[3]	valids[0x0]	24	1			T285	4		T286	7		T287	5
auto[1]	values[3]	valids[0x1]	15	1			T286	5		T288	5		T289	5
auto[1]	values[4]	valids[0x0]	43	1			T75	3		T76	4		T278	5
auto[1]	values[4]	valids[0x1]	23	1			T290	6		T291	3		T292	3
auto[1]	values[5]	valids[0x0]	33	1			T293	2		T277	8		T278	4
auto[1]	values[6]	valids[0x0]	38	1			T148	4		T294	4		T295	6
auto[1]	values[6]	valids[0x1]	9	1			T277	2		T296	2		T284	5
auto[1]	values[7]	valids[0x0]	13	1			T75	6		T277	3		T289	4
auto[1]	values[7]	valids[0x1]	6	1			T297	6		-	-		-	-
auto[1]	values[8]	valids[0x0]	211	1			T145	7		T148	7		T151	3
auto[1]	values[8]	valids[0x1]	70	1			T145	2		T151	5		T293	5