Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
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Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1778394 1 T2 1 T4 1156 T5 7686


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1615930 1 T2 1 T4 1156 T5 7686
auto[1] 162464 1 T9 11170 T11 4900 T18 1030


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 395837 1 T2 1 T4 347 T5 1005
auto[524288:1048575] 183746 1 T5 2404 T9 1417 T10 287
auto[1048576:1572863] 197173 1 T9 1 T10 287 T11 6084
auto[1572864:2097151] 125507 1 T5 532 T11 1786 T78 608
auto[2097152:2621439] 232692 1 T5 1314 T9 3 T10 2665
auto[2621440:3145727] 282939 1 T4 1 T5 1399 T9 7936
auto[3145728:3670015] 194225 1 T4 807 T5 607 T9 7544
auto[3670016:4194303] 166275 1 T4 1 T5 425 T9 4331


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 174595 1 T2 1 T4 6 T5 45
auto[1] 1603799 1 T4 1150 T5 7641 T9 19059


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1778394 1 T2 1 T4 1156 T5 7686


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 273310 1 T2 1 T4 347 T5 1005
auto[0] auto[0] auto[0:524287] auto[1] 122527 1 T9 6404 T11 2318 T18 1030
auto[0] auto[0] auto[524288:1048575] auto[0] 177903 1 T5 2404 T9 1165 T10 287
auto[0] auto[0] auto[524288:1048575] auto[1] 5843 1 T9 252 T11 1 T44 1989
auto[0] auto[0] auto[1048576:1572863] auto[0] 190419 1 T9 1 T10 287 T11 5830
auto[0] auto[0] auto[1048576:1572863] auto[1] 6754 1 T11 254 T44 32 T158 293
auto[0] auto[0] auto[1572864:2097151] auto[0] 125224 1 T5 532 T11 1531 T78 608
auto[0] auto[0] auto[1572864:2097151] auto[1] 283 1 T11 255 T95 1 T158 1
auto[0] auto[0] auto[2097152:2621439] auto[0] 224050 1 T5 1314 T9 2 T10 2665
auto[0] auto[0] auto[2097152:2621439] auto[1] 8642 1 T9 1 T11 6 T44 2486
auto[0] auto[0] auto[2621440:3145727] auto[0] 272455 1 T4 1 T5 1399 T9 6108
auto[0] auto[0] auto[2621440:3145727] auto[1] 10484 1 T9 1828 T11 2066 T95 253
auto[0] auto[0] auto[3145728:3670015] auto[0] 189532 1 T4 807 T5 607 T9 4862
auto[0] auto[0] auto[3145728:3670015] auto[1] 4693 1 T9 2682 T44 1049 T95 532
auto[0] auto[0] auto[3670016:4194303] auto[0] 163037 1 T4 1 T5 425 T9 4328
auto[0] auto[0] auto[3670016:4194303] auto[1] 3238 1 T9 3 T95 2 T159 267


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 174595 1 T2 1 T4 6 T5 45
auto[0] auto[0] auto[1] 1603799 1 T4 1150 T5 7641 T9 19059

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