Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.14	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	29	99	77.34

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	29	99	77.34	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2422

1

T2

4

T4

4

T5

16

auto[1]

886

1

T6

30

T56

18

T57

16

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	470	1			T25	18		T95	8		T58	26
values[1]	452	1			T8	34		T11	8		T28	24
values[2]	448	1			T6	30		T18	20		T244	22
values[3]	446	1			T198	20		T60	26		T160	24
values[4]	354	1			T84	2		T85	24		T204	20
values[5]	320	1			T56	18		T59	22		T44	30
values[6]	418	1			T4	4		T5	16		T9	16
values[7]	400	1			T2	4		T10	2		T43	12

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	444	1			T28	24		T57	16		T234	16
values[1]	538	1			T9	16		T10	2		T59	22
values[2]	316	1			T18	20		T94	12		T198	20
values[3]	244	1			T8	34		T60	26		T156	14
values[4]	472	1			T4	4		T244	22		T95	8
values[5]	458	1			T6	30		T11	8		T129	26
values[6]	434	1			T5	16		T86	4		T161	10
values[7]	402	1			T2	4		T43	12		T56	18

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	29	99	77.34	29

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[values[7]]	0	1	1
[auto[0]]	[values[4]]	[values[2]]	0	1	1
[auto[0]]	[values[5]]	[values[3]]	0	1	1
[auto[1]]	[values[0]]	[values[0]]	0	1	1
[auto[1]]	[values[0]]	[values[3]]	0	1	1
[auto[1]]	[values[0]]	[values[6]]	0	1	1
[auto[1]]	[values[1]]	[values[3] , values[4]]	--	--	2
[auto[1]]	[values[1]]	[values[7]]	0	1	1
[auto[1]]	[values[2]]	[values[1]]	0	1	1
[auto[1]]	[values[2]]	[values[4]]	0	1	1
[auto[1]]	[values[3]]	[values[4] , values[5]]	--	--	2
[auto[1]]	[values[3]]	[values[7]]	0	1	1
[auto[1]]	[values[4]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[4]]	[values[5]]	0	1	1
[auto[1]]	[values[5]]	[values[0] , values[1]]	--	--	2
[auto[1]]	[values[5]]	[values[3]]	0	1	1
[auto[1]]	[values[6]]	[values[0]]	0	1	1
[auto[1]]	[values[6]]	[values[2] , values[3]]	--	--	2
[auto[1]]	[values[6]]	[values[5] , values[6]]	--	--	2
[auto[1]]	[values[7]]	[values[0]]	0	1	1
[auto[1]]	[values[7]]	[values[2]]	0	1	1
[auto[1]]	[values[7]]	[values[4] , values[5]]	--	--	2

Covered bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	62	1			T220	6		T218	8		T206	20
auto[0]	values[0]	values[1]	60	1			T208	6		T237	30		T195	6
auto[0]	values[0]	values[2]	40	1			T27	22		T298	18		-	-
auto[0]	values[0]	values[3]	30	1			T70	24		T257	4		T259	2
auto[0]	values[0]	values[4]	70	1			T95	8		T229	8		T196	14
auto[0]	values[0]	values[5]	58	1			T25	18		T205	4		T168	8
auto[0]	values[0]	values[6]	24	1			T299	24		-	-		-	-
auto[0]	values[1]	values[0]	100	1			T28	24		T158	4		T174	8
auto[0]	values[1]	values[1]	14	1			T62	14		-	-		-	-
auto[0]	values[1]	values[2]	6	1			T24	4		T230	2		-	-
auto[0]	values[1]	values[3]	82	1			T8	34		T156	14		T226	8
auto[0]	values[1]	values[4]	30	1			T254	30		-	-		-	-
auto[0]	values[1]	values[5]	42	1			T11	8		T239	30		T203	4
auto[0]	values[1]	values[6]	26	1			T300	26		-	-		-	-
auto[0]	values[1]	values[7]	16	1			T301	16		-	-		-	-
auto[0]	values[2]	values[0]	26	1			T214	18		T302	8		-	-
auto[0]	values[2]	values[1]	10	1			T213	10		-	-		-	-
auto[0]	values[2]	values[2]	44	1			T18	20		T180	24		-	-
auto[0]	values[2]	values[3]	14	1			T303	4		T304	10		-	-
auto[0]	values[2]	values[4]	40	1			T244	22		T209	14		T179	4
auto[0]	values[2]	values[5]	82	1			T26	22		T159	20		T79	4
auto[0]	values[2]	values[6]	44	1			T305	28		T306	16		-	-
auto[0]	values[2]	values[7]	12	1			T210	6		T197	6		-	-
auto[0]	values[3]	values[0]	48	1			T181	26		T172	10		T307	12
auto[0]	values[3]	values[1]	66	1			T117	20		T188	10		T191	6
auto[0]	values[3]	values[2]	62	1			T198	20		T87	26		T242	16
auto[0]	values[3]	values[3]	32	1			T60	26		T97	6		-	-
auto[0]	values[3]	values[4]	22	1			T308	22		-	-		-	-
auto[0]	values[3]	values[5]	46	1			T116	8		T223	36		T216	2
auto[0]	values[3]	values[6]	72	1			T109	32		T187	20		T215	6
auto[0]	values[3]	values[7]	24	1			T160	24		-	-		-	-
auto[0]	values[4]	values[0]	26	1			T233	26		-	-		-	-
auto[0]	values[4]	values[1]	46	1			T89	20		T83	4		T309	14
auto[0]	values[4]	values[3]	26	1			T212	12		T249	14		-	-
auto[0]	values[4]	values[4]	66	1			T85	24		T238	8		T310	34
auto[0]	values[4]	values[5]	2	1			T84	2		-	-		-	-
auto[0]	values[4]	values[6]	20	1			T204	20		-	-		-	-
auto[0]	values[4]	values[7]	68	1			T194	16		T260	18		T183	14
auto[0]	values[5]	values[0]	6	1			T258	2		T261	4		-	-
auto[0]	values[5]	values[1]	66	1			T59	22		T44	30		T165	2
auto[0]	values[5]	values[2]	8	1			T29	2		T167	6		-	-
auto[0]	values[5]	values[4]	36	1			T221	26		T190	10		-	-
auto[0]	values[5]	values[5]	46	1			T96	20		T311	26		-	-
auto[0]	values[5]	values[6]	14	1			T23	4		T269	10		-	-
auto[0]	values[5]	values[7]	26	1			T110	20		T71	6		-	-
auto[0]	values[6]	values[0]	48	1			T312	22		T313	26		-	-
auto[0]	values[6]	values[1]	54	1			T9	16		T173	14		T222	20
auto[0]	values[6]	values[2]	54	1			T217	20		T175	8		T314	4
auto[0]	values[6]	values[3]	4	1			T207	4		-	-		-	-
auto[0]	values[6]	values[4]	46	1			T4	4		T315	4		T88	10
auto[0]	values[6]	values[5]	12	1			T268	12		-	-		-	-
auto[0]	values[6]	values[6]	78	1			T5	16		T86	4		T161	10
auto[0]	values[6]	values[7]	56	1			T177	8		T200	14		T248	34
auto[0]	values[7]	values[0]	12	1			T316	12		-	-		-	-
auto[0]	values[7]	values[1]	86	1			T10	2		T263	16		T192	16
auto[0]	values[7]	values[2]	14	1			T94	12		T317	2		-	-
auto[0]	values[7]	values[3]	6	1			T182	6		-	-		-	-
auto[0]	values[7]	values[4]	44	1			T61	22		T184	22		-	-
auto[0]	values[7]	values[5]	46	1			T129	26		T245	20		-	-
auto[0]	values[7]	values[6]	26	1			T211	4		T243	6		T111	16
auto[0]	values[7]	values[7]	76	1			T2	4		T43	12		T199	30
auto[1]	values[0]	values[1]	34	1			T58	26		T318	8		-	-
auto[1]	values[0]	values[2]	4	1			T319	4		-	-		-	-
auto[1]	values[0]	values[4]	18	1			T320	18		-	-		-	-
auto[1]	values[0]	values[5]	44	1			T265	24		T67	20		-	-
auto[1]	values[0]	values[7]	26	1			T247	26		-	-		-	-
auto[1]	values[1]	values[0]	32	1			T235	32		-	-		-	-
auto[1]	values[1]	values[1]	22	1			T162	12		T273	10		-	-
auto[1]	values[1]	values[2]	54	1			T170	14		T321	16		T186	24
auto[1]	values[1]	values[5]	20	1			T322	20		-	-		-	-
auto[1]	values[1]	values[6]	8	1			T236	8		-	-		-	-
auto[1]	values[2]	values[0]	44	1			T234	16		T166	28		-	-
auto[1]	values[2]	values[2]	2	1			T323	2		-	-		-	-
auto[1]	values[2]	values[3]	34	1			T64	34		-	-		-	-
auto[1]	values[2]	values[5]	30	1			T6	30		-	-		-	-
auto[1]	values[2]	values[6]	44	1			T227	24		T68	20		-	-
auto[1]	values[2]	values[7]	22	1			T65	22		-	-		-	-
auto[1]	values[3]	values[0]	38	1			T57	16		T324	22		-	-
auto[1]	values[3]	values[1]	18	1			T228	18		-	-		-	-
auto[1]	values[3]	values[2]	8	1			T224	8		-	-		-	-
auto[1]	values[3]	values[3]	2	1			T325	2		-	-		-	-
auto[1]	values[3]	values[6]	8	1			T246	8		-	-		-	-
auto[1]	values[4]	values[0]	2	1			T326	2		-	-		-	-
auto[1]	values[4]	values[1]	20	1			T274	20		-	-		-	-
auto[1]	values[4]	values[4]	50	1			T202	18		T262	32		-	-
auto[1]	values[4]	values[6]	10	1			T66	10		-	-		-	-
auto[1]	values[4]	values[7]	18	1			T264	18		-	-		-	-
auto[1]	values[5]	values[2]	20	1			T178	20		-	-		-	-
auto[1]	values[5]	values[4]	26	1			T327	26		-	-		-	-
auto[1]	values[5]	values[5]	30	1			T328	30		-	-		-	-
auto[1]	values[5]	values[6]	24	1			T63	24		-	-		-	-
auto[1]	values[5]	values[7]	18	1			T56	18		-	-		-	-
auto[1]	values[6]	values[1]	26	1			T329	26		-	-		-	-
auto[1]	values[6]	values[4]	24	1			T271	24		-	-		-	-
auto[1]	values[6]	values[7]	16	1			T272	16		-	-		-	-
auto[1]	values[7]	values[1]	16	1			T72	16		-	-		-	-
auto[1]	values[7]	values[3]	14	1			T276	14		-	-		-	-
auto[1]	values[7]	values[6]	36	1			T69	22		T189	2		T255	12
auto[1]	values[7]	values[7]	24	1			T231	24		-	-		-	-