Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.26	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	2	58	96.67

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	2	58	96.67	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	60	1			T5	2		T85	2		T89	4
auto[ReadAddrCrossIntoMailbox]	32	1			T5	8		T84	2		T89	2
auto[ReadAddrCrossOutOfMailbox]	28	1			T85	2		T89	6		T177	2
auto[ReadAddrCrossAllMailbox]	34	1			T5	2		T89	6		T177	2
auto[ReadAddrOutsideMailbox]	836	1			T4	4		T5	4		T6	14

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

495

1

T4

2

T5

8

T6

7

auto[1]

495

1

T4

2

T5

8

T6

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	184	1			T4	2		T5	4		T8	2
read_ops[0x0b]	136	1			T6	4		T8	2		T18	2
read_ops[0x3b]	148	1			T6	6		T18	2		T84	2
read_ops[0x6b]	162	1			T5	10		T18	2		T56	4
read_ops[0xbb]	180	1			T8	4		T244	4		T156	2
read_ops[0xeb]	180	1			T4	2		T5	2		T6	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	2	58	96.67	2

Automatically Generated Cross Bins for cr_all

Element holes

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	NUMBER	STATUS
[read_ops[0x3b]]	[auto[ReadAddrCrossOutOfMailbox]]	*	--	--	2

Covered bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	4	1			T223	1		T205	1		T214	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	4	1			T223	1		T205	1		T214	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	3	1			T5	1		T223	1		T205	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	3	1			T5	1		T223	1		T205	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	4	1			T257	1		T223	1		T197	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	4	1			T257	1		T223	1		T197	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	5	1			T117	4		T223	1		-	-
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	5	1			T117	4		T223	1		-	-
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	76	1			T4	1		T5	1		T8	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	76	1			T4	1		T5	1		T8	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	4	1			T263	1		T214	1		T249	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	4	1			T263	1		T214	1		T249	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	5	1			T117	1		T223	1		T263	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	5	1			T117	1		T223	1		T263	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	4	1			T117	1		T223	1		T317	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	4	1			T117	1		T223	1		T317	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T223	2		T343	1		-	-
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T223	2		T343	1		-	-
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	52	1			T6	2		T8	1		T18	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	52	1			T6	2		T8	1		T18	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	7	1			T117	2		T269	2		T298	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	7	1			T117	2		T269	2		T298	3
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T84	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T84	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	1	1			T223	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	1	1			T223	1		-	-		-	-
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	65	1			T6	3		T18	1		T25	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	65	1			T6	3		T18	1		T25	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	7	1			T5	1		T89	1		T176	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	7	1			T5	1		T89	1		T176	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	4	1			T5	2		T117	1		T197	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	4	1			T5	2		T117	1		T197	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	1	1			T223	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	1	1			T223	1		-	-		-	-
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	3	1			T5	1		T177	1		T223	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	3	1			T5	1		T177	1		T223	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	66	1			T5	1		T18	1		T56	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	66	1			T5	1		T18	1		T56	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	4	1			T89	1		T223	1		T214	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	4	1			T89	1		T223	1		T214	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	1	1			T177	1		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	1	1			T177	1		-	-		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	3	1			T89	2		T177	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	3	1			T89	2		T177	1		-	-
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	4	1			T89	2		T257	1		T223	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T89	2		T257	1		T223	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	78	1			T8	2		T244	2		T156	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	78	1			T8	2		T244	2		T156	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	4	1			T85	1		T256	1		T298	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	4	1			T85	1		T256	1		T298	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	2	1			T5	1		T89	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	2	1			T5	1		T89	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	2	1			T85	1		T89	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	2	1			T85	1		T89	1		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	1	1			T89	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	1	1			T89	1		-	-		-	-
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	81	1			T4	1		T6	2		T86	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	81	1			T4	1		T6	2		T86	1