Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	282127	1			T1	1		T2	1		T4	1
all_pins[1]	282127	1			T1	1		T2	1		T4	1
all_pins[2]	282127	1			T1	1		T2	1		T4	1
all_pins[3]	282127	1			T1	1		T2	1		T4	1
all_pins[4]	282127	1			T1	1		T2	1		T4	1
all_pins[5]	282127	1			T1	1		T2	1		T4	1
all_pins[6]	282127	1			T1	1		T2	1		T4	1
all_pins[7]	282127	1			T1	1		T2	1		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2256217	1			T1	8		T2	8		T4	8
values[0x1]	799	1			T19	37		T39	37		T41	6
transitions[0x0=>0x1]	601	1			T19	25		T39	27		T41	6
transitions[0x1=>0x0]	605	1			T19	25		T39	27		T41	6

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	282023	1			T1	1		T2	1		T4	1
all_pins[0]	values[0x1]	104	1			T19	5		T39	6		T40	3
all_pins[0]	transitions[0x0=>0x1]	80	1			T19	2		T39	6		T40	2
all_pins[0]	transitions[0x1=>0x0]	81	1			T19	3		T39	2		T41	1
all_pins[1]	values[0x0]	282022	1			T1	1		T2	1		T4	1
all_pins[1]	values[0x1]	105	1			T19	6		T39	2		T41	1
all_pins[1]	transitions[0x0=>0x1]	79	1			T19	5		T39	2		T41	1
all_pins[1]	transitions[0x1=>0x0]	71	1			T19	3		T39	6		T41	2
all_pins[2]	values[0x0]	282030	1			T1	1		T2	1		T4	1
all_pins[2]	values[0x1]	97	1			T19	4		T39	6		T41	2
all_pins[2]	transitions[0x0=>0x1]	73	1			T19	2		T39	6		T41	2
all_pins[2]	transitions[0x1=>0x0]	81	1			T19	3		T39	3		T40	8
all_pins[3]	values[0x0]	282022	1			T1	1		T2	1		T4	1
all_pins[3]	values[0x1]	105	1			T19	5		T39	3		T40	8
all_pins[3]	transitions[0x0=>0x1]	70	1			T19	2		T40	8		T340	4
all_pins[3]	transitions[0x1=>0x0]	63	1			T19	1		T39	2		T41	3
all_pins[4]	values[0x0]	282029	1			T1	1		T2	1		T4	1
all_pins[4]	values[0x1]	98	1			T19	4		T39	5		T41	3
all_pins[4]	transitions[0x0=>0x1]	77	1			T19	4		T39	4		T41	3
all_pins[4]	transitions[0x1=>0x0]	73	1			T19	1		T39	4		T40	5
all_pins[5]	values[0x0]	282033	1			T1	1		T2	1		T4	1
all_pins[5]	values[0x1]	94	1			T19	1		T39	5		T40	5
all_pins[5]	transitions[0x0=>0x1]	69	1			T39	2		T40	5		T341	1
all_pins[5]	transitions[0x1=>0x0]	83	1			T19	8		T39	3		T40	2
all_pins[6]	values[0x0]	282019	1			T1	1		T2	1		T4	1
all_pins[6]	values[0x1]	108	1			T19	9		T39	6		T40	2
all_pins[6]	transitions[0x0=>0x1]	88	1			T19	7		T39	5		T40	2
all_pins[6]	transitions[0x1=>0x0]	68	1			T19	1		T39	3		T40	1
all_pins[7]	values[0x0]	282039	1			T1	1		T2	1		T4	1
all_pins[7]	values[0x1]	88	1			T19	3		T39	4		T40	1
all_pins[7]	transitions[0x0=>0x1]	65	1			T19	3		T39	2		T40	1
all_pins[7]	transitions[0x1=>0x0]	85	1			T19	5		T39	4		T40	3