Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
66.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	49	79	61.72

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	49	79	61.72	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	348	1			T10	2		T160	24		T161	10
values[1]	366	1			T4	4		T84	2		T57	16
values[2]	394	1			T2	4		T8	34		T9	16
values[3]	572	1			T18	20		T129	26		T28	24
values[4]	546	1			T6	30		T94	12		T56	18
values[5]	454	1			T5	16		T11	8		T43	12
values[6]	308	1			T86	4		T162	12		T163	6
values[7]	320	1			T59	22		T95	8		T58	26

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	262	1			T6	30		T9	16		T161	10
values[1]	448	1			T4	4		T43	12		T61	22
values[2]	456	1			T129	26		T86	4		T57	16
values[3]	420	1			T25	18		T116	8		T58	26
values[4]	372	1			T11	8		T60	26		T28	24
values[5]	396	1			T2	4		T18	20		T56	18
values[6]	460	1			T8	34		T94	12		T59	22
values[7]	494	1			T5	16		T10	2		T160	24

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3244

1

T2

4

T4

4

T5

16

auto[1]

64

1

T6

6

T56

2

T58

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	49	79	61.72	49

Automatically Generated Cross Bins for cr_all

Element holes

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[2]]	*	--	--	8
[auto[1]]	[values[5]]	*	--	--	8

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0] , values[1]]	[values[0] , values[1]]	--	--	4
[auto[1]]	[values[0] , values[1]]	[values[3] , values[4]]	--	--	4
[auto[1]]	[values[0] , values[1]]	[values[6]]	--	--	2
[auto[1]]	[values[3]]	[values[0] , values[1] , values[2] , values[3] , values[4] , values[5] , values[6]]	--	--	7
[auto[1]]	[values[4]]	[values[1] , values[2]]	--	--	2
[auto[1]]	[values[4]]	[values[7]]	0	1	1
[auto[1]]	[values[6]]	[values[1] , values[2] , values[3] , values[4] , values[5] , values[6] , values[7]]	--	--	7
[auto[1]]	[values[7]]	[values[0] , values[1] , values[2]]	--	--	3
[auto[1]]	[values[7]]	[values[4] , values[5]]	--	--	2
[auto[1]]	[values[7]]	[values[7]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	24	1			T161	10		T164	14		-	-
auto[0]	values[0]	values[1]	44	1			T61	22		T26	22		-	-
auto[0]	values[0]	values[2]	28	1			T165	2		T166	20		T167	6
auto[0]	values[0]	values[3]	18	1			T116	8		T168	8		T169	2
auto[0]	values[0]	values[4]	20	1			T159	20		-	-		-	-
auto[0]	values[0]	values[5]	126	1			T44	30		T170	14		T171	26
auto[0]	values[0]	values[6]	10	1			T172	10		-	-		-	-
auto[0]	values[0]	values[7]	66	1			T10	2		T160	24		T173	14
auto[0]	values[1]	values[0]	8	1			T174	8		-	-		-	-
auto[0]	values[1]	values[1]	30	1			T4	4		T175	8		T176	14
auto[0]	values[1]	values[2]	32	1			T57	16		T69	16		-	-
auto[0]	values[1]	values[3]	58	1			T70	24		T177	8		T178	20
auto[0]	values[1]	values[4]	4	1			T179	4		-	-		-	-
auto[0]	values[1]	values[5]	104	1			T84	2		T180	24		T181	26
auto[0]	values[1]	values[6]	86	1			T182	6		T183	14		T184	22
auto[0]	values[1]	values[7]	32	1			T185	10		T186	22		-	-
auto[0]	values[2]	values[0]	52	1			T9	16		T187	20		T111	16
auto[0]	values[2]	values[1]	42	1			T188	10		T189	2		T190	10
auto[0]	values[2]	values[2]	30	1			T191	6		T192	16		T193	8
auto[0]	values[2]	values[3]	64	1			T27	22		T87	26		T194	16
auto[0]	values[2]	values[4]	46	1			T60	26		T195	6		T196	14
auto[0]	values[2]	values[5]	14	1			T2	4		T83	4		T197	6
auto[0]	values[2]	values[6]	78	1			T8	34		T198	20		T117	20
auto[0]	values[2]	values[7]	68	1			T199	30		T200	14		T201	10
auto[0]	values[3]	values[0]	22	1			T202	18		T203	4		-	-
auto[0]	values[3]	values[1]	72	1			T204	20		T205	4		T206	20
auto[0]	values[3]	values[2]	112	1			T129	26		T207	4		T208	6
auto[0]	values[3]	values[3]	52	1			T25	18		T209	14		T210	6
auto[0]	values[3]	values[4]	82	1			T28	24		T211	4		T212	12
auto[0]	values[3]	values[5]	64	1			T18	20		T213	10		T214	18
auto[0]	values[3]	values[6]	28	1			T215	6		T216	2		T72	16
auto[0]	values[3]	values[7]	138	1			T109	32		T158	4		T217	20
auto[0]	values[4]	values[0]	42	1			T6	24		T218	8		T219	10
auto[0]	values[4]	values[1]	78	1			T220	6		T221	26		T222	20
auto[0]	values[4]	values[2]	86	1			T223	36		T224	8		T225	20
auto[0]	values[4]	values[3]	58	1			T23	4		T226	8		T68	16
auto[0]	values[4]	values[4]	60	1			T156	14		T63	22		T227	24
auto[0]	values[4]	values[5]	54	1			T56	16		T228	18		T229	8
auto[0]	values[4]	values[6]	110	1			T94	12		T230	2		T64	28
auto[0]	values[4]	values[7]	38	1			T62	14		T231	24		-	-
auto[0]	values[5]	values[0]	10	1			T79	4		T232	6		-	-
auto[0]	values[5]	values[1]	76	1			T43	12		T71	6		T233	26
auto[0]	values[5]	values[2]	82	1			T234	16		T235	32		T236	8
auto[0]	values[5]	values[3]	70	1			T237	30		T238	8		T239	30
auto[0]	values[5]	values[4]	44	1			T11	8		T24	4		T88	10
auto[0]	values[5]	values[5]	12	1			T240	12		-	-		-	-
auto[0]	values[5]	values[6]	42	1			T241	20		T242	16		T243	6
auto[0]	values[5]	values[7]	118	1			T5	16		T244	22		T89	20
auto[0]	values[6]	values[0]	48	1			T245	20		T246	8		T247	20
auto[0]	values[6]	values[1]	48	1			T248	34		T249	14		-	-
auto[0]	values[6]	values[2]	22	1			T86	4		T162	12		T163	6
auto[0]	values[6]	values[3]	50	1			T250	4		T251	24		T252	22
auto[0]	values[6]	values[4]	78	1			T253	8		T254	30		T255	12
auto[0]	values[6]	values[5]	4	1			T256	4		-	-		-	-
auto[0]	values[6]	values[6]	34	1			T257	4		T258	2		T259	2
auto[0]	values[6]	values[7]	18	1			T260	18		-	-		-	-
auto[0]	values[7]	values[0]	44	1			T95	8		T261	4		T262	32
auto[0]	values[7]	values[1]	58	1			T85	24		T263	16		T264	18
auto[0]	values[7]	values[2]	50	1			T29	2		T96	20		T265	24
auto[0]	values[7]	values[3]	38	1			T58	20		T67	18		-	-
auto[0]	values[7]	values[4]	36	1			T266	12		T267	4		T268	12
auto[0]	values[7]	values[5]	10	1			T269	10		-	-		-	-
auto[0]	values[7]	values[6]	62	1			T59	22		T110	20		T65	18
auto[0]	values[7]	values[7]	10	1			T270	10		-	-		-	-
auto[1]	values[0]	values[2]	8	1			T166	8		-	-		-	-
auto[1]	values[0]	values[5]	2	1			T271	2		-	-		-	-
auto[1]	values[0]	values[7]	2	1			T66	2		-	-		-	-
auto[1]	values[1]	values[2]	6	1			T69	6		-	-		-	-
auto[1]	values[1]	values[5]	4	1			T272	2		T273	2		-	-
auto[1]	values[1]	values[7]	2	1			T186	2		-	-		-	-
auto[1]	values[3]	values[7]	2	1			T274	2		-	-		-	-
auto[1]	values[4]	values[0]	6	1			T6	6		-	-		-	-
auto[1]	values[4]	values[3]	4	1			T68	4		-	-		-	-
auto[1]	values[4]	values[4]	2	1			T63	2		-	-		-	-
auto[1]	values[4]	values[5]	2	1			T56	2		-	-		-	-
auto[1]	values[4]	values[6]	6	1			T64	6		-	-		-	-
auto[1]	values[6]	values[0]	6	1			T247	6		-	-		-	-
auto[1]	values[7]	values[3]	8	1			T58	6		T67	2		-	-
auto[1]	values[7]	values[6]	4	1			T65	4		-	-		-	-