Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1444

1

T1

14

T12

13

T7

17

auto[1]

1438

1

T1

15

T12

8

T7

15

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

759

1

T12

21

T13

31

T49

19

auto[1]

2123

1

T1

29

T7

32

T14

38

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2578

1

T1

29

T12

11

T7

32

auto[1]

304

1

T12

10

T13

11

T49

9

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	567	1			T1	7		T12	3		T7	8
valid[1]	590	1			T1	6		T12	7		T7	5
valid[2]	578	1			T1	4		T12	2		T7	5
valid[3]	562	1			T1	5		T12	6		T7	3
valid[4]	585	1			T1	7		T12	3		T7	11

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	35	1			T12	1		T13	3		T98	1
auto[0]	auto[0]	valid[0]	auto[1]	210	1			T1	2		T7	3		T14	1
auto[0]	auto[0]	valid[1]	auto[0]	48	1			T12	2		T13	1		T49	1
auto[0]	auto[0]	valid[1]	auto[1]	227	1			T1	3		T7	3		T14	12
auto[0]	auto[0]	valid[2]	auto[0]	49	1			T13	4		T101	1		T367	1
auto[0]	auto[0]	valid[2]	auto[1]	209	1			T7	3		T14	4		T50	1
auto[0]	auto[0]	valid[3]	auto[0]	50	1			T12	2		T13	5		T49	1
auto[0]	auto[0]	valid[3]	auto[1]	206	1			T1	4		T7	1		T14	6
auto[0]	auto[0]	valid[4]	auto[0]	48	1			T12	2		T49	1		T367	3
auto[0]	auto[0]	valid[4]	auto[1]	212	1			T1	5		T7	7		T14	5
auto[0]	auto[1]	valid[0]	auto[0]	42	1			T12	1		T49	2		T98	1
auto[0]	auto[1]	valid[0]	auto[1]	210	1			T1	5		T7	5		T14	1
auto[0]	auto[1]	valid[1]	auto[0]	44	1			T13	4		T98	1		T101	1
auto[0]	auto[1]	valid[1]	auto[1]	209	1			T1	3		T7	2		T14	2
auto[0]	auto[1]	valid[2]	auto[0]	42	1			T12	2		T49	3		T367	3
auto[0]	auto[1]	valid[2]	auto[1]	225	1			T1	4		T7	2		T14	3
auto[0]	auto[1]	valid[3]	auto[0]	49	1			T12	1		T13	2		T49	1
auto[0]	auto[1]	valid[3]	auto[1]	201	1			T1	1		T7	2		T14	3
auto[0]	auto[1]	valid[4]	auto[0]	48	1			T13	1		T49	1		T98	2
auto[0]	auto[1]	valid[4]	auto[1]	214	1			T1	2		T7	4		T14	1
auto[1]	auto[0]	valid[0]	auto[0]	33	1			T13	2		T49	2		T54	1
auto[1]	auto[0]	valid[1]	auto[0]	32	1			T12	4		T98	1		T99	1
auto[1]	auto[0]	valid[2]	auto[0]	21	1			T367	1		T368	1		T386	1
auto[1]	auto[0]	valid[3]	auto[0]	32	1			T12	2		T13	1		T49	1
auto[1]	auto[0]	valid[4]	auto[0]	32	1			T13	2		T49	2		T377	1
auto[1]	auto[1]	valid[0]	auto[0]	37	1			T12	1		T13	1		T49	2
auto[1]	auto[1]	valid[1]	auto[0]	30	1			T12	1		T98	2		T367	2
auto[1]	auto[1]	valid[2]	auto[0]	32	1			T13	1		T49	1		T101	1
auto[1]	auto[1]	valid[3]	auto[0]	24	1			T12	1		T13	2		T49	1
auto[1]	auto[1]	valid[4]	auto[0]	31	1			T12	1		T13	2		T101	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal