Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18252

1

T12

589

T13

778

T17

10

auto[1]

19968

1

T1

340

T7

458

T14

524

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31618

1

T1

340

T12

388

T7

458

auto[1]

6602

1

T12

201

T13

239

T17

4

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	19674	1			T1	169		T12	277		T7	238
others[1]	3197	1			T1	29		T12	54		T7	31
others[2]	3272	1			T1	40		T12	56		T7	44
others[3]	3604	1			T1	27		T12	54		T7	38
interest[1]	2087	1			T1	25		T12	34		T7	21
interest[4]	12931	1			T1	111		T12	182		T7	144
interest[64]	6386	1			T1	50		T12	114		T7	86

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	5907	1			T12	179		T13	280		T17	2
auto[0]	auto[0]	others[1]	1025	1			T12	35		T13	46		T17	2
auto[0]	auto[0]	others[2]	1027	1			T12	33		T13	37		T17	1
auto[0]	auto[0]	others[3]	1130	1			T12	36		T13	59		T49	32
auto[0]	auto[0]	interest[1]	618	1			T12	25		T13	32		T49	12
auto[0]	auto[0]	interest[4]	3872	1			T12	121		T13	189		T17	2
auto[0]	auto[0]	interest[64]	1943	1			T12	80		T13	85		T17	1
auto[0]	auto[1]	others[0]	10395	1			T1	169		T7	238		T14	281
auto[0]	auto[1]	others[1]	1614	1			T1	29		T7	31		T14	50
auto[0]	auto[1]	others[2]	1664	1			T1	40		T7	44		T14	38
auto[0]	auto[1]	others[3]	1861	1			T1	27		T7	38		T14	45
auto[0]	auto[1]	interest[1]	1121	1			T1	25		T7	21		T14	29
auto[0]	auto[1]	interest[4]	6872	1			T1	111		T7	144		T14	193
auto[0]	auto[1]	interest[64]	3313	1			T1	50		T7	86		T14	81
auto[1]	auto[0]	others[0]	3372	1			T12	98		T13	135		T17	2
auto[1]	auto[0]	others[1]	558	1			T12	19		T13	21		T17	1
auto[1]	auto[0]	others[2]	581	1			T12	23		T13	23		T49	25
auto[1]	auto[0]	others[3]	613	1			T12	18		T13	20		T49	11
auto[1]	auto[0]	interest[1]	348	1			T12	9		T13	9		T49	12
auto[1]	auto[0]	interest[4]	2187	1			T12	61		T13	77		T17	2
auto[1]	auto[0]	interest[64]	1130	1			T12	34		T13	31		T17	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal