Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	413	1			T19	18		T39	14		T41	4
all_values[1]	413	1			T19	18		T39	14		T41	4
all_values[2]	413	1			T19	18		T39	14		T41	4
all_values[3]	413	1			T19	18		T39	14		T41	4
all_values[4]	413	1			T19	18		T39	14		T41	4
all_values[5]	413	1			T19	18		T39	14		T41	4
all_values[6]	413	1			T19	18		T39	14		T41	4
all_values[7]	413	1			T19	18		T39	14		T41	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1756

1

T19

83

T39

42

T41

17

auto[1]

1548

1

T19

61

T39

70

T41

15

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1304

1

T19

49

T39

37

T41

13

auto[1]

2000

1

T19

95

T39

75

T41

19

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1872

1

T19

76

T39

61

T41

20

auto[1]

1432

1

T19

68

T39

51

T41

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	96	1			T19	2		T40	7		T340	4
all_values[0]	auto[0]	auto[0]	auto[1]	31	1			T19	1		T39	2		T41	2
all_values[0]	auto[0]	auto[1]	auto[0]	56	1			T19	3		T39	1		T41	1
all_values[0]	auto[0]	auto[1]	auto[1]	47	1			T19	2		T39	3		T40	2
all_values[0]	auto[1]	auto[0]	auto[1]	113	1			T19	5		T39	4		T41	1
all_values[0]	auto[1]	auto[1]	auto[1]	70	1			T19	5		T39	4		T40	2
all_values[1]	auto[0]	auto[0]	auto[0]	73	1			T19	2		T39	4		T41	1
all_values[1]	auto[0]	auto[0]	auto[1]	47	1			T19	2		T39	1		T41	1
all_values[1]	auto[0]	auto[1]	auto[0]	69	1			T19	3		T39	1		T40	2
all_values[1]	auto[0]	auto[1]	auto[1]	44	1			T19	3		T39	1		T40	3
all_values[1]	auto[1]	auto[0]	auto[1]	88	1			T19	5		T39	3		T40	3
all_values[1]	auto[1]	auto[1]	auto[1]	92	1			T19	3		T39	4		T41	2
all_values[2]	auto[0]	auto[0]	auto[0]	84	1			T19	5		T39	3		T40	3
all_values[2]	auto[0]	auto[0]	auto[1]	34	1			T19	1		T39	1		T341	1
all_values[2]	auto[0]	auto[1]	auto[0]	69	1			T19	3		T41	2		T40	4
all_values[2]	auto[0]	auto[1]	auto[1]	34	1			T19	1		T39	2		T41	1
all_values[2]	auto[1]	auto[0]	auto[1]	100	1			T19	3		T39	2		T40	8
all_values[2]	auto[1]	auto[1]	auto[1]	92	1			T19	5		T39	6		T41	1
all_values[3]	auto[0]	auto[0]	auto[0]	76	1			T19	2		T39	2		T40	3
all_values[3]	auto[0]	auto[0]	auto[1]	41	1			T19	3		T39	1		T40	1
all_values[3]	auto[0]	auto[1]	auto[0]	71	1			T19	2		T41	2		T40	2
all_values[3]	auto[0]	auto[1]	auto[1]	46	1			T19	2		T39	2		T41	1
all_values[3]	auto[1]	auto[0]	auto[1]	104	1			T19	6		T39	3		T41	1
all_values[3]	auto[1]	auto[1]	auto[1]	75	1			T19	3		T39	6		T40	3
all_values[4]	auto[0]	auto[0]	auto[0]	76	1			T19	3		T40	6		T341	1
all_values[4]	auto[0]	auto[0]	auto[1]	35	1			T19	1		T39	1		T41	1
all_values[4]	auto[0]	auto[1]	auto[0]	75	1			T19	2		T39	5		T40	6
all_values[4]	auto[0]	auto[1]	auto[1]	46	1			T19	2		T39	3		T41	1
all_values[4]	auto[1]	auto[0]	auto[1]	104	1			T19	6		T39	1		T41	1
all_values[4]	auto[1]	auto[1]	auto[1]	77	1			T19	4		T39	4		T41	1
all_values[5]	auto[0]	auto[0]	auto[0]	103	1			T19	6		T39	2		T41	1
all_values[5]	auto[0]	auto[1]	auto[0]	124	1			T19	3		T39	7		T40	7
all_values[5]	auto[1]	auto[0]	auto[1]	99	1			T19	8		T39	3		T41	3
all_values[5]	auto[1]	auto[1]	auto[1]	87	1			T19	1		T39	2		T40	2
all_values[6]	auto[0]	auto[0]	auto[0]	93	1			T19	4		T41	1		T40	6
all_values[6]	auto[0]	auto[0]	auto[1]	35	1			T19	2		T39	1		T40	1
all_values[6]	auto[0]	auto[1]	auto[0]	58	1			T39	5		T41	1		T40	3
all_values[6]	auto[0]	auto[1]	auto[1]	48	1			T19	4		T39	3		T40	1
all_values[6]	auto[1]	auto[0]	auto[1]	100	1			T19	4		T39	4		T41	2
all_values[6]	auto[1]	auto[1]	auto[1]	79	1			T19	4		T39	1		T40	2
all_values[7]	auto[0]	auto[0]	auto[0]	104	1			T19	5		T39	3		T41	2
all_values[7]	auto[0]	auto[0]	auto[1]	37	1			T19	2		T39	1		T40	1
all_values[7]	auto[0]	auto[1]	auto[0]	77	1			T19	4		T39	4		T41	2
all_values[7]	auto[0]	auto[1]	auto[1]	43	1			T19	1		T39	2		T341	1
all_values[7]	auto[1]	auto[0]	auto[1]	83	1			T19	5		T40	3		T342	4
all_values[7]	auto[1]	auto[1]	auto[1]	69	1			T19	1		T39	4		T40	6

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal