Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	211566	1			T1	4710		T2	26		T3	1
all_values[1]	211566	1			T1	4710		T2	26		T3	1
all_values[2]	211566	1			T1	4710		T2	26		T3	1
all_values[3]	211566	1			T1	4710		T2	26		T3	1
all_values[4]	211566	1			T1	4710		T2	26		T3	1
all_values[5]	211566	1			T1	4710		T2	26		T3	1
all_values[6]	211566	1			T1	4710		T2	26		T3	1
all_values[7]	211566	1			T1	4710		T2	26		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1690160

1

T1

37680

T2

208

T3

8

auto[1]

2368

1

T17

86

T40

67

T41

78

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1690439

1

T1

37675

T2

208

T3

8

auto[1]

2089

1

T1

5

T17

49

T13

5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	211151	1			T1	4710		T2	26		T3	1
all_values[0]	auto[0]	auto[1]	135	1			T17	3		T40	2		T41	7
all_values[0]	auto[1]	auto[0]	165	1			T17	8		T40	7		T41	4
all_values[0]	auto[1]	auto[1]	115	1			T17	2		T40	2		T41	9
all_values[1]	auto[0]	auto[0]	211140	1			T1	4710		T2	26		T3	1
all_values[1]	auto[0]	auto[1]	106	1			T17	2		T40	2		T41	5
all_values[1]	auto[1]	auto[0]	203	1			T17	8		T40	7		T41	13
all_values[1]	auto[1]	auto[1]	117	1			T17	7		T40	8		T352	6
all_values[2]	auto[0]	auto[0]	211139	1			T1	4710		T2	26		T3	1
all_values[2]	auto[0]	auto[1]	118	1			T17	2		T40	2		T41	9
all_values[2]	auto[1]	auto[0]	183	1			T17	8		T40	10		T41	2
all_values[2]	auto[1]	auto[1]	126	1			T17	4		T40	1		T41	1
all_values[3]	auto[0]	auto[0]	211143	1			T1	4710		T2	26		T3	1
all_values[3]	auto[0]	auto[1]	147	1			T17	4		T82	1		T40	6
all_values[3]	auto[1]	auto[0]	179	1			T17	3		T40	3		T41	6
all_values[3]	auto[1]	auto[1]	97	1			T17	4		T40	2		T41	1
all_values[4]	auto[0]	auto[0]	211124	1			T1	4710		T2	26		T3	1
all_values[4]	auto[0]	auto[1]	134	1			T17	1		T122	12		T76	3
all_values[4]	auto[1]	auto[0]	178	1			T17	6		T40	2		T41	3
all_values[4]	auto[1]	auto[1]	130	1			T17	5		T40	3		T41	4
all_values[5]	auto[0]	auto[0]	210952	1			T1	4705		T2	26		T3	1
all_values[5]	auto[0]	auto[1]	305	1			T1	5		T17	3		T13	5
all_values[5]	auto[1]	auto[0]	197	1			T17	7		T40	6		T41	5
all_values[5]	auto[1]	auto[1]	112	1			T17	5		T40	3		T41	3
all_values[6]	auto[0]	auto[0]	211157	1			T1	4710		T2	26		T3	1
all_values[6]	auto[0]	auto[1]	115	1			T17	1		T40	3		T41	2
all_values[6]	auto[1]	auto[0]	177	1			T17	6		T40	2		T41	5
all_values[6]	auto[1]	auto[1]	117	1			T17	4		T40	3		T41	10
all_values[7]	auto[0]	auto[0]	211192	1			T1	4710		T2	26		T3	1
all_values[7]	auto[0]	auto[1]	102	1			T17	2		T40	4		T41	6
all_values[7]	auto[1]	auto[0]	159	1			T17	9		T40	5		T41	3
all_values[7]	auto[1]	auto[1]	113	1			T40	3		T41	9		T352	1