Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
72.13	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	84	33	51	60.71

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	1	1	50.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	29	19	39.58	100	1	1	0
cr_modeXdummyXnum_lanes	36	4	32	88.89	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	1016	1			T7	24		T4	4		T9	8
auto[SpiFlashAddrCfg]	875	1			T2	11		T5	3		T6	6
auto[SpiFlashAddr3b]	1005	1			T2	4		T5	4		T8	12
auto[SpiFlashAddr4b]	940	1			T4	2		T6	3		T11	8

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3012

1

T2

15

T7

24

T4

6

auto[1]

824

1

T56

10

T57

26

T58

22

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2118

1

T2

15

T7

24

T5

4

auto[1]

1718

1

T4

6

T5

3

T6

5

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1426	1			T2	4		T7	24		T4	4
values[1]	65	1			T6	4		T11	2		T57	2
values[2]	185	1			T8	4		T93	4		T29	2
values[3]	155	1			T5	3		T6	2		T9	6
values[4]	152	1			T43	2		T73	4		T57	2
values[5]	209	1			T2	4		T5	4		T6	3
values[6]	188	1			T4	2		T8	12		T82	5
values[7]	210	1			T9	2		T82	7		T64	4
values[8]	1246	1			T2	7		T11	6		T12	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3260

1

T7

24

T4

6

T8

24

auto[1]

576

1

T2

15

T5

7

T6

9

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

3728

1

T2

15

T7

24

T4

6

write

108

1

T9

2

T29

2

T55

6

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

1942

1

T2

11

T4

2

T5

7

valids[0x1]

1894

1

T2

4

T7

24

T4

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	158	1			T43	2		T44	4		T45	4
internal_process_ops[0x5a]	150	1			T9	6		T12	4		T92	4
internal_process_ops[0x05]	144	1			T7	2		T4	2		T9	4
internal_process_ops[0x35]	174	1			T7	12		T4	2		T9	2
internal_process_ops[0x15]	150	1			T7	10		T12	2		T172	12
internal_process_ops[0x03]	305	1			T6	2		T11	6		T92	8
internal_process_ops[0x0b]	275	1			T2	4		T6	4		T12	2
internal_process_ops[0x3b]	268	1			T4	2		T5	3		T8	4
internal_process_ops[0x6b]	278	1			T2	3		T8	8		T9	2
internal_process_ops[0xbb]	287	1			T2	4		T5	4		T8	12
internal_process_ops[0xeb]	261	1			T2	4		T6	3		T82	7

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3800

1

T2

15

T7

24

T4

6

auto[1]

36

1

T56

4

T57

4

T58

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_upload

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3836

1

T2

15

T7

24

T4

6

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	29	19	39.58	29
Automatically Generated Cross Bins	48	29	19	39.58	29
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Element holes

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[write]	*	[auto[0]]	[auto[1]]	--	--	4
[auto[0]]	[write]	*	[auto[1]]	[auto[0]]	--	--	4
[auto[1]]	[read]	[auto[SpiFlashAddrDisabled]]	*	[auto[0]]	--	--	2
[auto[1]]	[write]	*	*	*	--	--	16

Uncovered bins

cp_is_flash	cp_is_write	cp_addr_mode	cp_addr_swap_en	cp_payload_swap_en	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[read]	[auto[SpiFlashAddrCfg] , auto[SpiFlashAddr3b] , auto[SpiFlashAddr4b]]	[auto[1]]	[auto[0]]	--	--	3

Covered bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

770

1

T7

24

T4

4

T9

8

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

210

1

T57

2

T58

2

T67

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

506

1

T8

12

T9

10

T11

8

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

174

1

T57

12

T58

6

T67

14

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

564

1

T8

12

T9

6

T11

8

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

194

1

T57

6

T58

6

T67

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

524

1

T4

2

T11

8

T12

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

210

1

T56

6

T57

2

T58

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

20

1

T62

2

T231

2

T61

8

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

16

1

T57

4

T58

2

T69

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

18

1

T9

2

T55

4

T61

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

6

1

T56

4

T281

2

-

-

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

30

1

T29

2

T196

6

T233

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

4

1

T67

2

T72

2

-

-

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

4

1

T55

2

T283

2

-

-

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

10

1

T67

2

T63

2

T68

2

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

171

1

T2

11

T5

3

T6

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

213

1

T2

4

T5

4

T137

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

192

1

T6

3

T82

12

T137

13

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	4	32	88.89	4

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Uncovered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[1]]	[valids[0x0]]	0	1	1
[auto[1]]	[values[0] , values[1]]	[valids[0x0]]	--	--	2
[auto[1]]	[values[2]]	[valids[0x1]]	0	1	1

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	368	1			T11	8		T29	2		T26	20
auto[0]	values[0]	valids[0x1]	1002	1			T7	24		T4	4		T9	18
auto[0]	values[1]	valids[0x1]	56	1			T11	2		T57	2		T58	4
auto[0]	values[2]	valids[0x0]	104	1			T8	4		T93	4		T29	2
auto[0]	values[2]	valids[0x1]	50	1			T231	2		T224	6		T68	2
auto[0]	values[3]	valids[0x0]	50	1			T58	4		T284	2		T241	4
auto[0]	values[3]	valids[0x1]	70	1			T9	6		T43	2		T92	8
auto[0]	values[4]	valids[0x0]	100	1			T43	2		T57	2		T231	8
auto[0]	values[4]	valids[0x1]	24	1			T73	4		T173	2		T218	2
auto[0]	values[5]	valids[0x0]	106	1			T8	8		T11	8		T62	4
auto[0]	values[5]	valids[0x1]	54	1			T120	4		T91	2		T173	2
auto[0]	values[6]	valids[0x0]	80	1			T4	2		T8	12		T62	4
auto[0]	values[6]	valids[0x1]	40	1			T73	2		T264	2		T67	2
auto[0]	values[7]	valids[0x0]	102	1			T9	2		T45	8		T120	2
auto[0]	values[7]	valids[0x1]	38	1			T64	4		T67	4		T194	6
auto[0]	values[8]	valids[0x0]	654	1			T43	2		T64	2		T92	2
auto[0]	values[8]	valids[0x1]	362	1			T11	6		T12	2		T44	2
auto[1]	values[0]	valids[0x1]	56	1			T2	4		T122	3		T83	3
auto[1]	values[1]	valids[0x1]	9	1			T6	4		T285	5		-	-
auto[1]	values[2]	valids[0x0]	31	1			T122	4		T286	4		T287	4
auto[1]	values[3]	valids[0x0]	14	1			T5	3		T286	4		T285	3
auto[1]	values[3]	valids[0x1]	21	1			T6	2		T288	6		T289	6
auto[1]	values[4]	valids[0x0]	19	1			T290	2		T291	7		T292	4
auto[1]	values[4]	valids[0x1]	9	1			T293	4		T294	5		-	-
auto[1]	values[5]	valids[0x0]	41	1			T2	4		T5	4		T6	3
auto[1]	values[5]	valids[0x1]	8	1			T295	6		T296	2		-	-
auto[1]	values[6]	valids[0x0]	45	1			T82	5		T76	7		T293	7
auto[1]	values[6]	valids[0x1]	23	1			T293	4		T297	5		T298	3
auto[1]	values[7]	valids[0x0]	51	1			T82	7		T286	7		T77	6
auto[1]	values[7]	valids[0x1]	19	1			T287	6		T299	7		T300	6
auto[1]	values[8]	valids[0x0]	177	1			T2	7		T82	5		T137	5
auto[1]	values[8]	valids[0x1]	53	1			T137	11		T76	8		T301	11