Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
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Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
36.36 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 16 2 14 87.50
Crosses 72 54 18 25.00


Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_busy_bit 2 1 1 50.00 100 1 1 2
cp_is_host_read 2 0 2 100.00 100 1 1 2
cp_other_status 8 0 8 100.00 100 1 1 8
cp_sw_read_while_csb_active 2 0 2 100.00 100 1 1 2
cp_wel_bit 2 1 1 50.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all_except_csb 64 48 16 25.00 100 1 1 0
cr_busyXwelXcsb 8 6 2 25.00 100 1 1 0


Summary for Variable cp_busy_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_busy_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1746217 1 T2 16723 T7 63152 T4 3504


Summary for Variable cp_is_host_read

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_is_host_read

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1674221 1 T2 16723 T7 47308 T4 3252
auto[1] 71996 1 T7 15844 T4 252 T12 1280


Summary for Variable cp_other_status

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for cp_other_status

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:524287] 347871 1 T2 2230 T7 10111 T4 628
auto[524288:1048575] 245251 1 T2 2359 T7 5980 T4 213
auto[1048576:1572863] 160949 1 T2 505 T7 16857 T4 426
auto[1572864:2097151] 192019 1 T2 682 T7 4376 T4 848
auto[2097152:2621439] 194797 1 T2 3543 T7 1637 T4 295
auto[2621440:3145727] 212956 1 T7 6354 T5 2732 T6 18737
auto[3145728:3670015] 213518 1 T2 13 T7 13215 T4 602
auto[3670016:4194303] 178856 1 T2 7391 T7 4622 T4 492


Summary for Variable cp_sw_read_while_csb_active

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_sw_read_while_csb_active

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 87075 1 T2 50 T7 15974 T4 315
auto[1] 1659142 1 T2 16673 T7 47178 T4 3189


Summary for Variable cp_wel_bit

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for cp_wel_bit

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1746217 1 T2 16723 T7 63152 T4 3504


Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 48 16 25.00 48


Automatically Generated Cross Bins for cr_all_except_csb

Element holes
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * * -- -- 16
[auto[1]] * * * -- -- 32


Covered bins
cp_busy_bitcp_wel_bitcp_other_statuscp_is_host_readCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0:524287] auto[0] 293408 1 T2 2230 T7 3064 T4 466
auto[0] auto[0] auto[0:524287] auto[1] 54463 1 T7 7047 T4 162 T12 1280
auto[0] auto[0] auto[524288:1048575] auto[0] 241946 1 T2 2359 T7 4242 T4 213
auto[0] auto[0] auto[524288:1048575] auto[1] 3305 1 T7 1738 T172 128 T44 507
auto[0] auto[0] auto[1048576:1572863] auto[0] 155560 1 T2 505 T7 14131 T4 426
auto[0] auto[0] auto[1048576:1572863] auto[1] 5389 1 T7 2726 T172 1481 T90 2
auto[0] auto[0] auto[1572864:2097151] auto[0] 191756 1 T2 682 T7 4373 T4 758
auto[0] auto[0] auto[1572864:2097151] auto[1] 263 1 T7 3 T4 90 T172 147
auto[0] auto[0] auto[2097152:2621439] auto[0] 192331 1 T2 3543 T7 30 T4 295
auto[0] auto[0] auto[2097152:2621439] auto[1] 2466 1 T7 1607 T172 12 T90 1
auto[0] auto[0] auto[2621440:3145727] auto[0] 211810 1 T7 5711 T5 2732 T6 18737
auto[0] auto[0] auto[2621440:3145727] auto[1] 1146 1 T7 643 T172 425 T173 48
auto[0] auto[0] auto[3145728:3670015] auto[0] 208886 1 T2 13 T7 11139 T4 602
auto[0] auto[0] auto[3145728:3670015] auto[1] 4632 1 T7 2076 T172 1301 T89 514
auto[0] auto[0] auto[3670016:4194303] auto[0] 178524 1 T2 7391 T7 4618 T4 492
auto[0] auto[0] auto[3670016:4194303] auto[1] 332 1 T7 4 T172 2 T44 1


Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 6 2 25.00 6


Automatically Generated Cross Bins for cr_busyXwelXcsb

Element holes
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [auto[1]] * -- -- 2
[auto[1]] * * -- -- 4


Covered bins
cp_busy_bitcp_wel_bitcp_sw_read_while_csb_activeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] 87075 1 T2 50 T7 15974 T4 315
auto[0] auto[0] auto[1] 1659142 1 T2 16673 T7 47178 T4 3189

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